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data sheet october 2001 orca ? orli10g quad 2.5 gbits/s 10 gbits/s, and 12.5 gbits/s line interface fpsc introduction agere systems inc. has developed a new orca series 4 based fpsc which combines a high-speed line interface with a flexible fpga logic core. built on the series 4 reconfigurable embedded system-on- chips (soc) architecture, the orli10g consists of an oif standard (oif 99.102.5) compliant xsbi or oif-sfi4-01.0 sfi-4, 10 gbits/s or 12.5 gbits/s transmit and 10 gbits/s or 12.5 gbits/s receive line interface. both transmit and receive interfaces con- sist of 16-bit lvds data up to 850 mbits/s, integrated transmit and receive programmable plls for data rate conversions between the line-side and system- side data rates, and a programmable logic interface at the system end for use with sonet/sdh, ether- net, or otn/digital wrapper with strong fec system device data standards. in addition to the embedded functionality, the device will include up to 400k of usable fpga gates. the line interface includes logic to divide the data rate down to 212 mhz or less (1/4 line rate) or 106 mhz or less (1/8 line rate) for transfer to the fpga logic. the orli10g is designed to connect directly to agere?s 10 gbits/s ttrn0110g mux and trcv0110g demux or agere?s 12.5 gbits/s ttrn0126 mux and trcv01126 demux on the line side, as well as other industry- standard devices. the programmable logic interface on the system side allows for direct connection to a 10 gbits/s ethernet mac, a 10 gbits/s sonet/sdh framer/data engine, or a 10 gbits/s/12.5 gbits/s digi- tal wrapper/fec framer/data engine. for 10 gbits/s ethernet, the orli10g supports the physical coding sublayer (pcs), interfaces to the physical media attachment (pma), and connects to the system interface (host or switch) for the proposed ieee ? 802.3ae 10 gbits/s serial lan phy. the orli10g fpsc is a high-speed programmable device for 10g/s data solutions. it can be used as the interface between the line interface and the system interface in a variety of emerging networks, including 10 gbits/s sonet/sdh (oc-192/stm-48), 10 gbits/s optical transport networks (otn) using digital wrapper and strong fec, or 10 gbits/s ether- net. other functions include use in quad oc-48/ stm-16 sonet/sdh systems, interfaces between quad oc-48/stm-16 and oc-192/stm-64 compo- nents, and use as a generic data transfer mechanism between two devices at 10 gbits/s rates. data is received at the line interface and then sent to either a 4-bit or 8-bit serial-to-parallel converter. on the trans- mit interface, either a 4-bit or 8-bit parallel-to-serial converter is used. thus, the data rate at the internal fpga interface is either 1/4 or 1/8 the line rate. the programmable plls on the orli10g provide for great flexibility in handling clock rate conversion due to differing amounts of overhead bits in various sys- tem data standards. for example, the orli10g can divide down the sts-192/stm-64 sonet/sdh data line rate of 622 mhz by 4 to synchronize with a 155 mhz system clock, or the 12.5 gbits/s super- fec data line rate of 781 mhz can be divided by 8 to 98 mhz system clock or by 8 x 4/5 to provide a 78 mhz system data rate. table 1. orca orli10g?available fpga logic * 192 user i/os for the 416 pbgam package and 316 user i/os for the 680 pbgam package are available out of the 432 possible user i/os. note: the embedded core and interface are not included in the above gate counts. the usable gate counts range from a logic-only gate count to a gate count assuming 20% of the pfus/slics being used as rams. the logic-only gate count includes each pfu/slic (counted as 108 gates/pfu), including 12 gates per lut/ff pair (eight per pfu), and 12 gates per slic/ff pair (one per pfu). each of the four pio groups are counted as 16 gates (three ffs, fast-capture latch, output logic, clk, and i/o buffers). pfus u sed as ram are counted at four gates per bit, with each pfu capable of implementing a 32 x 4 ram (or 512 gates) per pfu. embedded block ram (ebr) is counted as four gates per bit, plus each block has an additional 25k gates. 7k gates are used for each pll a nd 50k gates for the embedded system bus and microprocessor interface logic. both the ebr and plls are conservatively utilized in the gate count calculations. device pfu rows pfu columns total pfus user i/os * luts ebr blocks ebr bits (k) usable gates (k) orli10g 36 36 1296 432 10,368 12 111 380?800
table of contents contents page contents page 2 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s introduction..................................................................1 embedded function features .....................................4 intellectual property features......................................4 programmable features..............................................4 programmable logic system features .......................6 description...................................................................7 fpsc definition ........................................................7 fpsc overview ........................................................7 fpsc gate counting ................................................7 fpga/embedded core interface ..............................7 orca foundry development system ......................7 fpsc design kit .......................................................8 fpga logic overview...............................................8 plc logic .................................................................8 programmable i/o.....................................................9 routing......................................................................9 system-level features..............................................10 microprocessor interface ........................................10 system bus.............................................................10 phase-locked loops ..............................................10 embedded block ram............................................10 configuration...........................................................11 additional information .............................................11 orli10g overview ...................................................11 device layout .........................................................11 10g mode ...............................................................11 2.5g mode ..............................................................12 receive path details .................................................15 line interface ..........................................................15 demux ...................................................................15 onboard receive plls...........................................15 transmit path details ................................................17 mux ........................................................................17 onboard transmit plls..........................................17 line interface ..........................................................17 orli10g demultiplexer (rx) detail ..........................19 orli10g multiplexer (tx) detail ...............................25 orli10g embedded plls........................................31 orli10g embedded programmable plls specifications ........................................................... 32 orli10g reset requirements................................. 32 line interface circuit specifications ......................... 33 power supply decoupling lc circuit ..................... 33 xgmii orca 4e receive analysis .......................... 34 xgmii considerations ............................................ 34 absolute maximum ratings...................................... 35 recommended operating conditions ...................... 35 embedded core lvds i/o ....................................... 36 lvds receiver buffer requirements..................... 37 timing characteristics .............................................. 38 receive input data interface.................................. 38 transmit sts-48/sts-192 (2.5g/10g) data outputs ..................................................................... 39 input/output buffer measurement conditions (non-lvds buffer) ................................................... 40 lvds buffer characteristics..................................... 41 termination resistor .............................................. 41 lvds driver buffer capabilities ............................. 41 pin information ......................................................... 42 package pinouts .................................................... 47 package thermal characteristics summary ............ 65 ja ........................................................................ 65 jc ........................................................................ 65 jc ........................................................................ 65 jb ........................................................................ 65 fpsc maximum junction temperature ................. 65 package thermal characteristics............................. 66 heat sink vendors for bga packages ..................... 66 package coplanarity ................................................ 66 package parasitics ................................................... 67 package outline diagrams....................................... 68 terms and definitions ............................................ 68 416-pin pbgam..................................................... 69 680-pin pbgam..................................................... 70 hardware ordering information ................................ 71 software ordering information ................................. 71
agere systems inc. 3 data sheet october 2001 table of contents (continued) list of figures page list of tables page 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s figure 1. orca orli10g block diagram ...............13 figure 2. 10g (single-channel) and 2.5g (quad-channel) modes .........................................14 figure 3. orli10g embedded core receive path diagram .........................................................16 figure 4. orli10g embedded core transmit path diagram .................................................................18 figure 5. demultiplexer output data structure ........20 figure 6. demultiplexer serial-to-parallel conversion ? divide by 8, 10g mode .....................21 figure 7. demultiplexer serial-to-parallel conversion ? divide by 4, 10g mode .....................22 figure 8. demultiplexer serial-to-parallel conversion ? divide by 8, 2.5g mode ....................23 figure 9. demultiplexer serial-to-parallel conversion ? divide by 4, 2.5g mode ....................24 figure 10. multiplexer input data structure ..............26 figure 11. multiplexer parallel-to-serial conversion ? divide by 8, 10g mode .....................27 figure 12. multiplexer parallel-to-serial conversion ? divide by 4, 10g mode .....................28 figure 13. multiplexer parallel-to-serial conversion ? divide by 8, 2.5g mode ....................29 figure 14. multiplexer parallel-to-serial conversion ? divide by 4, 2.5g mode ....................30 figure 15. orli10g programmable pll block diagram .................................................................31 figure 16. sample power supply filter network for analog li power supply pins .................................33 figure 17. simplified xgmii block diagram .............34 figure 18. receive input data timing ......................38 figure 19. transmit output data timing ..................39 figure 20. ac test loads ..........................................40 figure 21. output buffer delays ...............................40 figure 22. input buffer delays ..................................40 figure 23. lvds driver and receiver and associated internal components ..............................................41 figure 24. lvds driver and receiver ......................41 figure 25. lvds driver ............................................41 figure 26. package parasitics ..................................67 table 1. orca orli10g ? available fpga logic ... 1 table 2. programmable pll specifications ............ 32 table 3. orli10g reset requirements .................. 32 table 4. hstl input requirements to fpga .......... 35 table 5. absolute maximum ratings ....................... 35 table 6. recommended operating conditions ....... 35 table 7. driver dc data ............................................ 36 table 8. driver ac data ............................................ 36 table 9. driver power consumption ........................ 36 table 10. receiver ac data ..................................... 37 table 11. receiver power consumption ................. 37 table 12. receiver dc data ..................................... 37 table 13. lvds operating parameters ................... 37 table 14. receive data input timing ...................... 38 table 15. transmit data output timing .................. 39 table 16. fpga common-function pin description ............................................................ 42 table 17. fpsc function pin description ............... 45 table 18. embedded core/fpga interface signal description ............................................................ 46 table 19. orca programmable i/os summary ...... 47 table 20. pbga pinout table ................................. 48 table 21. orca orli10g plastic package thermal guidelines ............................................... 66 table 22. heat sink vendors ................................... 66 table 23. . orca orli10g package parasitics .... 67 table 24. device type options ............................... 71 table 25. temperature options ............................... 71 table 26. package options ..................................... 71 table 27. package matrix (speed grade) ............... 71
4 4 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s embedded function features provides a line interface-to-interface with various system standards such as oc-192/stm-64 sonet/ sdh, quad oc-48/stm-16 10 gbits/s ethernet, and 10 gbits/s otn (digital wrapper/strong fec) or 12.5 gbits/s superfec. embedded plls with programmable m/n multiplication/division values provide for flexible data rate conversion between line side and system side. line side provides for 16-bit lvds data with multiple line frequencies supported up to 850 mhz, depending on system standard. line side interface, including timing and jitter specifications, compliant to oif 99.102.5 standard. receive side interface can be split into four separate asynchronous 2.5 gbits/s interfaces (4-bit lvds data interface for each) with a separate clock for each for transfer to the fpga logic. data and clock rates divided by 4 or 8 for use in fpga logic. direct interface to agere ? s 10 gbits/s mux (ttrn0110g) and demux (trcv0110g) or 12.5 gbits/s mux (ttrn01126) and demux (trcv01126) for xsbi, sfi-4, or superfec applications. lvds i/os compliant with eia ? -644 support hot insertion. all embedded lvds i/os include both input and output on-board termination to allow high-speed operation. low-power lvds buffers. intellectual property features programmable logic provides a variety of yet-to-be standardized interface functions, including the following ip core functions: 10 gbits/s ethernet as defined by ieee 802.3ae: ? xgmii for interfacing to 10 gbits/s ethernet macs. xgmii is a 156 mhz double data rate parallel short-reach (typically less than 2 in.) interconnect interface. ? elastic store buffers for clock domain transfer to/ from the xgmii interface. ? x 59 + x 39 + x 1 scrambler/descrambler for 10 gbits/s ethernet. ? 64b/66b encoders/decoders for 10 gbits/s ethernet. pos-phy4 interface for 10 gbits/s sonet/sdh and otn systems and some 10 gbits/s ethernet systems. quad 2.5 gbits/s sonet/sdh to 10 gbits/s sonet/ sdh mux/demux functions. 66-bit word aligner and 64b/66b receive path decoder, 64b/66b transmit path encoder, and 66b/64b transmit path conversion for ethernet overhead bits. programmable features high-performance programmable logic: ? 0.16 m 7-level metal technology. ? internal performance of >250 mhz. ? 400k usable system gates. ? meets multiple i/o interface standards. ? 1.5 v operation (30% less power than 1.8 v operation) translates to greater performance. traditional i/o selections: ? lvttl and lvcmos (3.3 v, 2.5 v, and 1.8 v) i/os. ? per pin-selectable i/o clamping diodes provide 3.3 v pci compliance. ? individually programmable drive capability: 24 ma sink/12 ma source, 12 ma sink/6 ma source, or 6 ma sink/3 ma source. ? two slew rates supported (fast and slew limited). ? fast-capture input latch and input flip-flop (ff) latch for reduced input setup time and zero hold time. ? fast open-drain drive capability. ? capability to register 3-state enable signal. ? off-chip clock drive capability. ? two input function generator in output path. new programmable high-speed i/o: ? single-ended: gtl, gtl+, pecl, sstl3/2 (class i & ii), hstl (class i, iii, iv), zbt, and ddr. ? double-ended: lvds, bused-lvds, lvpecl. programmable parallel termination (100 ? ) also supported for these i/os. ? customer-defined: ability to substitute arbitrary standard cell i/o to meet fast-moving standards. new capability to (de)multiplex i/o signals: ? new ddr on both input and output at rates up to 311 mhz (622 mhz effective rate). ? new 2x and 4x downlink and uplink capability per i/o (i.e., 50 mhz internal to 200 mhz i/o).
agere systems inc. 5 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s programmable features (continued) enhanced twin-quad programmable function unit (pfu): ? eight 16-bit look-up tables (luts) per pfu. ? nine user registers per pfu, one following each lut, and organized to allow two nibbles to act independently, plus one extra for arithmetic opera- tions. ? new register control in each pfu has two inde- pendent programmable clocks, clock enables, local set/reset, and data selects. ? new lut structure allows flexible combinations of lut4, lut5, new lut6, 4 1 mux, new 8 1 mux, and ripple mode arithmetic functions in the same pfu. ? 32 x 4 ram per pfu, configurable as single- or dual-port. create large, fast ram/rom blocks (128 x 8 in only eight pfus) using the slic decoders as bank drivers. ? soft-wired luts (swl) allow fast cascading of up to three levels of lut logic in a single pfu through fast internal routing which reduces routing congestion and improves speed. ? flexible fast access to pfu inputs from routing. ? fast-carry logic and routing to all four adjacent pfus for nibble-wide, byte-wide, or longer arith- metic functions, with the option to register the pfu carry-out. abundant high-speed buffered and nonbuffered routing resources provide 2x average speed improvements over previous architectures. hierarchical routing optimized for both local and global routing with dedicated routing resources. this results in faster routing times with predictable and efficient performance. slic provides eight 3-stable buffers, up to a 10-bit decoder, and pal ? -like and-or-invert (aoi) in each programmable logic cell. new 200 mhz embedded quad-port ram blocks, two read ports, two write ports, and two sets of byte lane enables. each embedded ram block can be configured as: ? 1 ? 512 x 18 (quad-port, two read/two write) with optional built-in arbitration. ? 1 ? 256 x 36 (dual-port, one read/one write). ? 1 ? 1k x 9 (dual-port, one read/one write). ? 2 ? 512 x 9 (dual-port, one read/one write for each). ? 2 rams with arbitrary number of words whose sum is 512 or less by 18 (dual-port, one read/one write). ? supports joining of ram blocks. ? two 16 x 8-bit content addressable memory (cam) support. ? fifo 512 x 18, 256 x 36, 1k x 9, or dual 512 x 9. ? constant multiply (8 x 16 or 16 x 8). ? dual variable multiply (8 x 8). embedded 32-bit internal system bus plus 4-bit parity interconnects fpga logic, microprocessor interface (mpi), embedded ram blocks, and embedded standard cell blocks with 100 mhz bus performance. included are built-in system registers that act as the control and status center for the device. built-in testability: ? full boundary scan ( ieee 1149.1 and draft 1149.2 jtag) for the programmable i/os only. ? programming and readback through boundary- scan port compliant to ieee draft 1532:d1.7. ? ts_all testability function to 3-state all i/o pins. ? new temperature-sensing diode. improved built-in clock management with programmable phase-locked loops (pplls) provides optimum clock modification and conditioning for phase, frequency, and duty cycle from 20 mhz up to 420 mhz. multiplication of input frequency up to 64x and division of input frequency down to 1/64x possible. new cycle stealing capability allows a typical 15% to 40% internal speed improvement after final place and route. this feature also enables compliance with many setup/hold and clock to out i/o specifications and may provide reduced ground bounce for output buses by allowing flexible delays of switching output buffers.
6 6 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s programmable logic system features pci local bus compliant for fpga i/os. improved powerpc ? / powerquicc 860 and powerpc / powerquicc ii mpc8260 high-speed synchronous microprocessor interface can be used for configuration, readback, device control, and device status, as well as for a general-purpose interface to the fpga logic, rams, and embedded standard-cell blocks. glueless interface to synchronous powerpc processors with user- configurable address space provided. new embedded amba ? specification 2.0 ahb system bus ( arm ? processor) facilitates communication among the microprocessor interface, configuration logic, embedded block ram, fpga logic, and embedded standard cell blocks. variable-size bused readback of configuration data capability with the built-in microprocessor interface and system bus. internal, 3-state, and bidirectional buses with simple control provided by the slic. new clock routing structures for global and local clocking significantly increases speed and reduces skew (<200 ps for or4e4). new local clock routing structures allow creation of localized clock trees. two new edge clock structures allow up to six high- speed clocks on each edge of the device for improved setup/hold and clock to out performance. new double-data rate (ddr) and zero-bus turn- around (zbt) memory interfaces support the latest high-speed memory interfaces. new 2x/4x uplink and downlink i/o capabilities interface high-speed external i/os to reduced-speed internal logic. orca foundry development system software. supported by industry-standard cae tools for design entry, synthesis, simulation, and timing analysis. meets universal test and operations phy interface for atm (utopia) levels 1, 2, and 3 as well as pos-phy3. also meets proposed specifications for utopia level 4 and pos-phy4 for 10 gbits/s interfaces. meets pos-phy3 (2.5 gbits/s) and pos-phy4 (10 gbits/s) interface standards for packet-over- sonet as defined by the saturn group.
agere systems inc. 7 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s description fpsc definition fpscs, or field-programmable system chips, are devices that combine field-programmable logic with asic or mask-programmed logic on a single device. fpscs provide the time to market and the flexibility of fpgas, the design effort savings of using soft intellec- tual property (ip) cores, and the speed, design density, and economy of asics. fpsc overview agere ? s series 4 fpscs are created from series 4 orca fpgas. to create a series 4 fpsc, several col- umns of programmable logic cells (see fpga logic overview section for fpga logic details) are added to an embedded logic core. other than replacing some fpga gates with asic gates, at greater than 10:1 effi- ciency, none of the fpga functionality is changed ? all of the series 4 fpga capability is retained: embedded block rams, mpi, pcms, boundary scan, etc. the col- umns of programmable logic are replaced at the right of the device, allowing pins from the replaced columns to be used as i/o pins for the embedded core. the remainder of the device pins retain their fpga func- tionality. the embedded cores can take many forms and gener- ally come from agere ? s asic libraries. other offerings allow customers to supply their own core functions for the creation of custom fpscs. fpsc gate counting the total gate count for an fpsc is the sum of its embedded core (standard-cell/asic gates) and its fpga gates. because fpga gates are generally expressed as a usable range with a nominal value, the total fpsc gate count is sometimes expressed in the same manner. standard-cell asic gates are, however, 10 to 25 times more silicon-area efficient than fpga gates. therefore, an fpsc with an embedded function is gate equivalent to an fpga with a much larger gate count. fpga/embedded core interface the interface between the fpga logic and the embed- ded core has been enhanced to allow for a greater number of interface signals than on previous fpsc architectures. compared to bringing embedded core signals off-chip, this on-chip interface is much faster and requires less power. all of the delays for the inter- face are precharacterized and accounted for in the orca foundry development system. series 4 based fpscs expand this interface by provid- ing a link between the embedded block and the multi- master 32-bit system bus in the fpga logic. this sys- tem bus allows the core easy access to many of the fpga logic functions, including the embedded block rams and the microprocessor interface. clock spines also can pass across the fpga/embed- ded core boundary. this allows for fast, low-skew clocking between the fpga and the embedded core. many of the special signals from the fpga, such as done and global set/reset, are also available to the embedded core, making it possible to fully integrate the embedded core with the fpga as a system. for even greater system flexibility, fpga configuration rams are available for use by the embedded core. this allows for user-programmable options in the embedded core, in turn allowing for greater flexibility. multiple embedded core configurations may be designed into a single device with user-programmable control over which configurations are implemented, as well as the capability to change core functionality sim- ply by reconfiguring the device. orca foundry development system the orca foundry development system is used to process a design from a netlist to a configured fpga. this system is used to map a design onto the orca architecture and then place and route it using orca foundry ? s timing-driven tools. the development sys- tem also includes interfaces to, and libraries for, other popular cae tools for design entry, synthesis, simula- tion, and timing analysis. the orca foundry development system interfaces to front-end design entry tools and provides the tools to produce a configured fpga. in the design flow, the user defines the functionality of the fpga at two points in the design flow: design entry and the bit stream gen- eration stage. recent improvements in orca foundry allow the user to provide timing requirement informa- tion through logical preferences only; thus, the designer is not required to have physical knowledge of the implementation.
8 8 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s description (continued) following design entry, the development system ? s map, place, and route tools translate the netlist into a routed fpga. a floor planner is available for layout feedback and control. a static timing analysis tool is provided to determine design speed, and a back-annotated netlist can be created to allow simulation and timing. timing and simulation output files from orca foundry are also compatible with many third-party analysis tools. a bit stream generator is then used to generate the configuration data which is loaded into the fpgas internal configuration ram, embedded block ram, and/or fpsc memory. when using the bit stream generator, the user selects options that affect the functionality of the fpga. com- bined with the front-end tools, orca foundry pro- duces configuration data that implements the various logic and routing options discussed in this data sheet. fpsc design kit development is facilitated by an fpsc design kit which, together with orca foundry and third-party synthesis and simulation engines, provides all software and documentation required to design and verify an fpsc implementation. included in the kit are the fpsc configuration manager, synopsys smart model ? , and complete online documentation. the kit's software cou- ples with orca foundry, providing a seamless fpsc design environment. more information can be obtained by visiting the orca website or contacting a local sales office, both listed on the last page of this docu- ment. fpga logic overview the orca series 4 architecture is a new generation of sram-based programmable devices from agere. it includes enhancements and innovations geared toward today ? s high-speed systems on a single chip. designed with networking applications in mind, the series 4 family incorporates system-level features that can further reduce logic requirements and increase system speed. orca series 4 devices contain many new patented enhancements and are offered in a vari- ety of packages and speed grades. the hierarchical architecture of the logic, clocks, rout- ing, ram, and system-level blocks create a seamless merge of fpga and asic designs. modular hardware and software technologies enable system-on-chip inte- gration with true plug-and-play design implementation. the architecture consists of four basic elements: pro- grammable logic cells (plcs), programmable i/o cells (pios), embedded block rams (ebrs), and system- level features. these elements are interconnected with a rich routing fabric of both global and local wires. an array of plcs are surrounded by common interface blocks which provide an abundant interface to the adja- cent plcs or system blocks. routing congestion around these critical blocks is eliminated by the use of the same routing fabric implemented within the pro- grammable logic core. each plc contains a pfu, slic, local routing resources, and configuration ram. most of the fpga logic is performed in the pfu, but decoders, pal -like functions, and 3-state buffering can be performed in the slic. the pios provide device inputs and outputs and can be used to register signals and to perform input demultiplexing, output multiplex- ing, uplink and downlink functions, and other functions on two output signals. large blocks of 512 x 18 quad- port ram complement the existing distributed pfu memory. the ram blocks can be used to implement ram, rom, fifo, multiplier, and cam. some of the other system-level functions include the mpi, plls, and the embedded system bus (esb). plc logic each pfu within a plc contains eight 4-input (16-bit) luts, eight latches/ffs, and one additional flip-flop that may be used independently or with arithmetic func- tions. the pfu is organized in a twin-quad fashion; two sets of four luts and ffs that can be controlled indepen- dently. each pfu has two independent programmable clocks, clock enables, local set/reset, and data selects. luts may also be combined for use in arithmetic func- tions using fast-carry chain logic in either 4-bit or 8-bit modes. the carry-out of either mode may be registered in the ninth ff for pipelining. each pfu may also be configured as a synchronous 32 x 4 single- or dual-port ram or rom. the ffs (or latches) may obtain input from lut outputs or directly from invertible pfu inputs, or they can be tied high or tied low. the ffs also have programmable clock polarity, clock enables, and local set/reset.
agere systems inc. 9 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s description (continued) the slic is connected from plc routing resources and from the outputs of the pfu. it contains eight 3-state, bidirectional buffers, and logic to perform up to a 10-bit and function for decoding, or an and-or with optional invert to perform pal -like functions. the 3-state drivers in the slic and their direct connections from the pfu outputs make fast, true, 3-state buses possible within the fpga, reducing required routing and allowing for real-world system performance. programmable i/o the series 4 pio addresses the demand for the flexi- bility to select i/os that meet system interface require- ments. i/os can be programmed in the same manner as in previous orca devices, with the additional new features that allow the user the flexibility to select new i/o types that support high-speed interfaces. each pio contains four programmable i/o pads and is interfaced through a common interface block to the fpga array. the pio is split into two pairs of i/o pads with each pair having independent clock enables, local set/reset, and global set/reset. on the input side, each pio contains a programmable latch/flip-flop which enables very fast latching of data from any pad. the combination provides for very low setup requirements and zero hold times for signals coming on-chip. it may also be used to demultiplex an input signal, such as a multiplexed address/data signal, and register the sig- nals without explicitly building a demultiplexer with a pfu. on the output side of each pio, an output from the plc array can be routed to each output flip-flop, and logic can be associated with each i/o pad. the output logic associated with each pad allows for multiplexing of output signals and other functions of two output sig- nals. the output ff, in combination with output signal multi- plexing, is particularly useful for registering address signals to be multiplexed with data, allowing a full clock cycle for the data to propagate to the output. the out- put buffer signal can be inverted, and the 3-state con- trol can be made active-high, active-low, or always enabled. in addition, this 3-state signal can be regis- tered or nonregistered. the series 4 i/o logic has been enhanced to include modes for speed uplink and downlink capabilities. these modes are supported through shift register logic, which divides down incoming data rates or multi- plies up outgoing data rates. this new logic block also supports high-speed ddr mode requirements where data is clocked into and out of the i/o buffers on both edges of the clock. the new programmable i/o cell allows designers to select i/os which meet many new communication stan- dards, permitting the device to hook up directly without any external interface translation. they support tradi- tional fpga standards as well as high-speed, single- ended, and differential-pair signaling (as shown in table 1). based on a programmable, bank-oriented i/o ring architecture, designs can be implemented using 3.3 v, 2.5 v, 1.8 v, and 1.5 v referenced output levels. routing the abundant routing resources of the series 4 archi- tecture are organized to route signals individually or as buses with related control signals. both local and glo- bal signals utilize high-speed buffered and nonbuffered routes. one plc segmented (x1), six plc segmented (x6), and bused half-chip (xhl) routes are patterned together to provide high connectivity with fast software routing times and high-speed system performance. eight fully distributed primary clocks are routed on a low-skew, high-speed distribution network and may be sourced from dedicated i/o pads, plls, or the plc logic. secondary and edge-clock routing are available for fast regional clock or control signal routing for both internal regions and on device edges. secondary clock routing can be sourced from any i/o pin, plls, or the plc logic. the improved routing resources offer great flexibility in moving signals to and from the logic core. this flexibil- ity translates into an improved capability to route designs at the required speeds when the i/o signals have been locked to specific pins.
10 10 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s system-level features the series 4 also provides system-level functionality by means of its microprocessor interface, embedded system bus, quad-port embedded block rams, universal programmable phase-locked loops, and the addition of highly tuned networking specific phase- locked loops. these functional blocks allow for easy glueless system interfacing and the capability to adjust to varying conditions in today ? s high-speed networking systems. microprocessor interface the mpi provides a glueless interface between the fpga and powerpc microprocessors. programmable in 8-, 16-, and 32-bit interfaces with optional parity to the motorola ? powerpc 860 bus, it can be used for configuration and readback, as well as for fpga con- trol and monitoring of fpga status. all mpi transac- tions utilize the series 4 embedded system bus at 66 mhz performance. a system-level microprocessor interface to the fpga user-defined logic following configuration, through the system bus, including access to the embedded block ram and general user-logic, is provided by the mpi. the mpi supports burst data read and write transfers, allowing short, uneven transmission of data through the interface by including data fifos. transfer accesses can be single beat (1 x 4 bytes or less), 4-beat (4 x 4 bytes), 8-beat (8 x 2 bytes), or 16-beat (16 x 1 bytes). system bus an on-chip, multimaster, 8-bit system bus with 1-bit parity facilitates communication among the mpi, con- figuration logic, fpga control, and status registers, embedded block rams, as well as user logic. utilizing the amba specification rev 2.0 ahb protocol, the embedded system bus offers arbiter, decoder, master, and slave elements. the system bus control registers can provide control to the fpga such as signaling for reprogramming, reset functions, and pll programming. status registers monitor init, done, and system bus errors. an interrupt controller is integrated to provide up to eight possible interrupt resources. bus clock generation can be sourced from the microprocessor interface clock, configuration clock (for slave configuration modes), internal oscillator, user clock from routing, or port clock (for jtag configuration modes). phase-locked loops up to eight plls are provided on each series 4 device, with four plls generally provided for fpscs. program- mable plls can be used to manipulate the frequency, phase, and duty cycle of a clock signal. each ppll is capable of manipulating and conditioning clocks from 20 mhz to 420 mhz. frequencies can be adjusted from 1/8x to 8x, the input clock frequency. each programma- ble pll provides two outputs that have different multi- plication factors but can have the same phase relationships. duty cycles and phase delays can be adjusted in 12.5% of the clock period increments. an automatic input buffer delay compensation mode is available for phase delay. each ppll provides two out- puts that can have programmable (12.5% steps) phase differences. additional highly tuned and characterized, dedicated phase-locked loops (dplls) are included to ease sys- tem designs. these dplls meet itu-t g.811 primary- clocking specifications and enable system designers to very tightly target specified clock conditioning not tradi- tionally available in the universal pplls. initial dplls are targeted to low-speed networking ds1 and e1, and also high-speed sonet/sdh networking sts-3 and stm-1 systems. embedded block ram new 512 x 18 quad-port ram blocks are embedded in the fpga core to significantly increase the amount of memory and complement the distributed pfu memo- ries. the ebrs include two write ports, two read ports, and two byte lane enables which provide four-port operation. optional arbitration between the two write ports is available, as well as direct connection to the high-speed system bus. additional logic has been incorporated to allow significant flexibility for fifo, constant multiply, and two-variable multiply functions. the user can configure fifo blocks with flexible depths of 512k, 256k, and 1k, including asynchronous and synchronous modes and programmable status and error flags. multiplier capabilities allow a multiple of an 8-bit number with a 16-bit fixed coefficient or vice versa (24-bit output), or a multiply of two 8-bit numbers (16-bit output). on-the-fly coefficient modifications are available through the second read/write port. two 16 x 8-bit cams per embedded block can be implemented in single match, multiple match, and clear modes. the ebrs can also be preloaded at device configuration time.
agere systems inc. 11 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s system-level features (continued) configuration the fpgas functionality is determined by internal con- figuration ram. the fpgas internal initialization/con- figuration circuitry loads the configuration data at powerup or under system control. the configuration data can reside externally in an eeprom or any other storage media. serial eeproms provide a simple, low pin-count method for configuring fpgas. the ram is loaded by using one of several configura- tion modes. supporting the traditional master/slave serial, master/slave parallel, and asynchronous periph- eral modes, the series 4 also utilizes its microproces- sor interface and embedded system bus to perform both programming and readback. daisy chaining of multiple devices and partial reconfiguration are also permitted. other configuration options include the initialization of the embedded-block ram memories and fpsc memory as well as system bus options and bit stream error checking. programming and readback through the jtag (ieee 1149.2 ) port is also available meeting in-system programming (isp) standards ( ieee 1532 draft). additional information contact your local agere representative for additional information regarding the orca series 4 fpga devices, or visit our website at: http://www.agere.com/orca orli10g overview device layout the orli10g fpsc provides a high-speed transmit and receive line interface combined with fpga logic. the device is based on the 1.5 v or4e4 fpga. the orli10g consists of an embedded backplane trans- ceiver core and a full or4e4 36x36 fpga array. the orli10g is a line interface device that contains an fpga base array, a 10 gbits/s line interface block, and programmable plls to do the overhead clock rate con- versions on a single monolithic chip. the embedded portion includes: line interface: this consists of a 16-bit lvds receive data bus and a 16-bit lvds transmit bus operating up to 850 mbits/s per input/output pair. each 4-bit lvds i/o has a high-speed lvds clock (operating up to 850 mhz) associated with it. mux/demux: this performs the muxing and demuxing between the high-speed line interface data operating at the line rate and system data oper- ating at 1/4 or 1/8 the line rate. on-board plls: this is used to align system-side data with the line-side data, which is at a slightly higher data bandwidth than the system data because of the addition of overhead due to encoding. figure 1 shows the orli10g block diagram. 10g mode the orli10g can operate in one of two data modes: 10g mode or quad 2.5g mode. in 10g (or single-channel) mode, all 16 lvds transmit data outputs are assumed to be one data bus with one lvds clock provided off chip for the data. likewise, all 16 lvds receive data inputs are assumed to be one data bus with one lvds input clock provided for the data. transmit path in 10g mode, the transmit data from the fpga logic is passed to the embedded core as a single 128- or 64-bit bus. an off-chip transmit reference clock is divided down in the core by 8 (for 128-bit to 16-bit mux) or by 4 (for 64-bit to 16-bit mux). all four transmit clock out- puts are therefore synchronized.
12 12 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g overview (continued) receive path the 16-bit receive data is demuxed in the embedded core to a single 128-bit or 64-bit data bus and passed to the fpga logic. the lowest-order lvds input clock (rx_clk_in[0]) is used as the receive clock for all 16 data bits (the other three lvds input clock pairs should be tied low). this clock is divided down in the core by 8 (for 16-bit to 128-bit demux) or by 4 (for 16-bit to 64-bit demux) and passed to the fpga logic with the data. the orli10g supports transmit and receive data rates up to 850 mbits/s. therefore, the total data rate for this mode is 850 mbits/s x 16 or 13.6 gbits/s. 2.5g mode in 2.5g (or quad-channel) mode, the 16 lvds transmit data outputs are assumed to be four 4-bit data buses with four lvds clocks provided off chip for each data bus. likewise, the 16 lvds receive data inputs are assumed to be four independent 4-bit data buses with four lvds asynchronous input clocks provided for each data bus. transmit path in 2.5g mode, the transmit data from the fpga logic is passed to the embedded core as four separate 32- or 16-bit buses. a separate clock for each of the four bus- ses is also passed to the core. an off-chip transmit ref- erence clock is divided down in the core by 8 (for each 32 to 8-bit mux) or by 4 (for each 16 to 4 mux). this divided down clock is used to resynchronize the output data and clocks. all four transmit clock outputs are therefore synchronized. receive path each of the four 4-bit receive data buses are demuxed in the embedded core to one of four independent 32- or 16-bit data buses and passed to the fpga logic. the four receive clock inputs are divided down in the core by 8 (for each 4- to 32-bit demux) or by 4 (for each 4- to 16-bit demux), and each divided clock is passed to the fpga logic with its associated data bus. all four data paths act as separate data interfaces that are asynchronous to each other. the orli10g supports transmit and receive data rates up to 850 mbits/s. therefore, the total data rate each of the quad channels is 850 mbits/s x 4 or 3.4 gbits/s. figure 2 shows a representation of the 10g and 2.5g modes in both transmit and receive directions.
agere systems inc. 13 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g overview (continued) 1018(f) figure 1. orca orli10g block diagram embedded core fpga logic (400k gates) transmit plls reference clock transmit data 16 x 622 or 16 x 645 or 16 x 667 or 64:16 mux or 128:16 mux transmit clock receive plls 16:64 demux or 16:128 demux receive data 16 x 622 or 16 x 645 or 16 x 667 or four 2.5 gbit rxclks 64-bit or 128-bit rxclk 64-bit or 128-bit txclk (167 mhz ? 78 mhz) (167 mhz ? 78 mhz) system interface: ? pos-phy 4 ? xgmii ? 156 mhz pecl (oc-48/stm-16 sonet/sdh) ? user defined 16 x 781 mbits/s 16 x 781 mbits/s 2 2
14 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g overview (continued) 1335(f) figure 2. 10g (single-channel) and 2.5g (quad-channel) modes data 128 or 64 2.5g mode receive path core lvds data 32 or 16 fpga lvds clock lvds data core fpga clock 32 or 16 4 demux fpga core lvds data 16 rx_clk_in[0] rx_clk_in[31:1] clock 1 data 4 data mux transmit path 10g mode div by 8 or div by 4 div by 8 div by 8 mux lvds 16 tx_clk_in core 128 or 64 fpga data unused reference data transmit path mux mux mux 32 or 16 data 32 or 16 data 32 or 16 data lvds data 4 lvds data 4 lvds data 4 div by 8 or div by 4 1 1 lvds clock lvds data clock 32 or 16 4 demux data div by 8 or div by 4 1 1 lvds clock lvds data clock 32 or 16 4 demux data div by 8 or div by 4 1 1 lvds clock lvds data clock 32 or 16 4 demux data div by 8 or div by 4 1 1 receive path demux clock div by 4 tx[1:2]vcop 2 div by 4 tx_clk_in reference clock tx_clk_out[3:0] lvds clocks tx_clk8_in[3:0] 4
agere systems inc. 15 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s receive path details in the receive path, the orli10g embedded core can be broken down into three sections: the high-speed line interface, the demultiplexer, and the receive-side on- board plls. note that both transmit and receive plls are in addition to the four programmable plls (pplls) in the fpga portion of the orli10g. line interface in the receive path, 16-bit data and associated clocks are inputs to the line interface. typical data rates are expected to range from 622 mbits/s to 850 mbits/s for most applications. the 16-bit lvds input data bus is actually composed of four 4-bit data buses with one clock for each 4-bit data bus. in the 10g mode, all four input clocks are tied together internal to the device and driven by the lowest-order input clock. in 2.5g mode, the four clocks may be asynchronous to each other. the orli10g uses lvds (low-voltage differential sig- naling) drivers/receivers, which are intended to provide point-to-point connection between the orli10g and optical transceiver (mux/demux) parts. the lvds inputs are hot-swap compatible and can connect to other vendor ? s lvds i/o buffers. the lvds inputs are terminated with a 100 ? resistor to improve perfor- mance. the receive line interface on the orli10g can connect to devices that are compliant to either the xsbi stan- dard or the sfi-4 standard. the major difference for these standards is that for xsbi ( ieee 802.3ae version 2.1), the least significant bit [0] is received first after deserialization by the external demux device, whereas sfi-4 receives the most significant bit first. in some cases, bits [15:0] on the orli10g should be con- nected to bits [0:15] on the device to which the orli10g device interfaces to. an example of this is the pcs ip core in the orli10g when the orli10g is connected to an xsbi version 2.1 device. it should be noted that ieee 802.3ae version 3.1 swaps xsbi so that the most significant bit is received first, thus requiring that bits [0:15] on the orli10g be connected directly to bits [0:15] on the xsbi device. demux the demultiplexer takes the high-speed line data and clocks and converts the data and clock to rates appro- priate for transfer to the fpga logic. the demultiplexer supports two modes of operation: divide-by-8 10g (or single channel): the demultiplexer converts the incoming 16 bits of data at 622 mbits/s to 850 mbits/s into 128 bits at 78 mbits/s to 106 mbits/s. the incoming clocks are divided by 8. 2.5g (or quad channel): the demultiplexer converts the incoming four bits of data at 622 mbits/s to 850 mbits/s into 32 bits at 78 mbits/s to 106 mbits/s. the associated clock is also divided by 8. this is repeated four times with each 4-bit data/clock group assumed to be asynchronous to the others. divide-by-4 10g (or single channel): the demultiplexer converts the incoming 16 bits of data at 622 mbits/s to 850 mbits/s into 64 bits at 156 mbits/s to 212 mbits/s. the incoming clocks are divided by 4. 2.5g (or quad channel): the demultiplexer converts the incoming 4 bits of data at 622 mbits/s to 850 mbits/s into 16 bits at 156 mbits/s to 212 mbits/s. the associated clock is also divided by 4. this is repeated four times with each 4-bit data/clock group assumed to be asynchronous to the others. onboard receive plls the function of the onboard plls is to align the system data with the line data which will be at a slightly higher rate owing to the addition of the overhead bits. there are two plls on the receive path. the input to the first pll, rx1_pll (see figure 3), is the divided down low- est-order clock from the demultiplexer. the rx1_pll generates a clock with a user-defined frequency ratio of m/n to the divided clock. this clock would generally be used to compensate for different data rates due to overhead bits. m and n can independently be set from 1 to 8. the rx2_pll also takes its input from the divided down clock and is used to provide a balanced divided clock across the fpga-embedded core interface. both plls have delay loops which compensate for routing delays to the embedded core/fpga logic inter- face for minimum clock skew. in addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period. the selection of the demux width (and corresponding clock division value), the rx1_pll m and n values, and the additional skew for rx1_pll and rx2_pll are specified by the user in a gui interface provided in the orli10g design kit. a detailed block diagram of the receive path in shown in figure 3.
16 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s receive path details (continued) 1333(f) figure 3. orli10g embedded core receive path diagram 128 to 16 mux or 64 to 16 mux data rx_dat_in 16 clock rx_clk_in 4 fpga logic divide by 8 mode rx_dat_out[127:96] rx_dat_out[95:64] rx_dat_out[63:32] rx_dat_out[31:0] or rx_enb_out[3:0] divide by 4 mode rx_dat_out[111:96] rx_dat_out[79:64] rx_dat_out[47:32] rx_dat_out[15:0] rx_clk8_out[0] rx_clk8_out[1] rx_clk8_out[2] rx_clk8_out[3] div by 8 or div by 4 orli10g core rx1_pll (m/n) rx2_pll (x1) rx1_vcop (x m/n clock) rx_lock rx2_vcop (x 1 clock) div by 8 or div by 4 div by 8 or div by 4 div by 8 or div by 4 rx_enb_out[3:0] rx1_vco rx2_vco
agere systems inc. 17 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s transmit path details in the transmit path, the orli10g embedded core can be broken down into three sections: the multiplexer, the transmit side onboard plls, and the high-speed line interface. note that both transmit and receive plls are in addition to the four programmable plls (pplls) in the fpga portion of the orli10g. mux the multiplexer takes data from the fpga logic and multiplexes the data to rates for transfer by the high- speed line interface. the multiplexer supports two modes of operation: multiplex-by-8 the multiplexer converts the incoming 128 bits of data at 78 mbits/s to 106 mbits/s into 16 bits at 622 mbits/s to 850 mbits/s. the incoming transmit reference clock is divided by 8. multiplex-by-4 10g (or single channel): the multiplexer converts the incoming 64 bits of data at 156 mbits/s to 212 mbits/s into 16 bits at 622 mbits to 850 mbits/s. the transmit reference clock is divided by 4. onboard transmit plls the function of the onboard plls is to align the system data with the line data which will be at a slightly higher rate owing to the addition of the overhead bits. there are two plls on the transmit path. the input to the first pll, tx1_pll (see figure 4), is the divided down transmit reference clock from the multiplexer. the tx1_pll generates a clock with a user-defined fre- quency ratio of m/n to the divided clock. this clock would generally be used to compensate for different data rates due to overhead bits. m and n can be inde- pendently set from 1 to 8. the tx2_pll also takes its input reference from the divided down reference clock and is used to provide a balanced divided clock across the fpga-embedded core interface. both plls have delay loops which compensate for routing delays to the embedded core/fpga logic inter- face for minimum clock skew. in addition, the user can specify an additional skew on each clock in increments of 1/8 the clock period. the selection of the mux width (and corresponding clock division value), the tx1_pll m and n values, and the additional skew for tx1_pll and tx2_pll are specified by the user in a gui interface provided in the orli10g design kit. a detailed block diagram of the transmit path in shown in figure 4. in 10 gbit mode, either tx1_vcop or tx2_vcop must be used to clock tx_dat_in[127:0] that is transmitted to the embedded block. these plls can also be bypassed, where the divided transmit ref- erence clock is sent directly to the fpga. in 2.5 gbit mode, tx_clk8_in[3:0] is used to clock data transmit- ted to the embedded block. line interface in the transmit path, 16-bit data and associated clocks are outputs from the line interface. typical data rates are expected to range from 622 mbits/s to 850 mbits/s for most applications. the 16-bit lvds output data bus is actually composed of four 4-bit data buses with one clock for each 4-bit data bus. on the transmit side, these clocks will all be synchronized. the orli10g uses lvds (low-voltage differential signaling) drivers/receivers, which are intended to provide point- to-point connection between the orli10g and optical transceiver (mux/demux) parts. the lvds drivers are hot-swap compatible and can connect to other vendor ? s lvds i/o buffers. the lvds drivers are terminated with a 100 ? resistor to improve performance. the transmit line interface on the orli10g can con- nect to devices that are compliant to either the xsbi standard or the sfi-4 standard. the major difference for these standards is that for xsbi, the least signifi- cant bit [0] is transferred first after serialization by the external mux device, whereas sfi-4 transmits the most significant bit first. in some cases, bits [15:0] on the orli10g should be connect to bits [0:15] on the device to which the orli10g device interfaces to. an example of this is the pcs ip core in the orli10g when the orli10g is connected to an xsbi version 2.1 device. it should be noted that ieee 802.3ae version 3.1 swaps xsbi so that the most significant bit is trans- ferred first, thus requiring that bits [0:15] on the orli10g be connected directly to bits [0:15] on the xsbi device.
18 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s transmit path details (continued) 1332(f) figure 4. orli10g embedded core transmit path diagram 128 to 16 mux or 64 to 16 mux data tx_dat_out 16 clock tx_clk8_out 4 transmit reference clock fpga logic divide by 8 mode tx_dat_in[127:96] tx_dat_in[95:64] tx_dat_in[63:32] tx_dat_in[31:0] or tx_enb_in[3:0] divide by 4 mode tx_dat_in[111:96] tx_dat_in[79:64] tx_dat_in[47:32] tx_dat_in[15:0] 10g 2.5g tx_clk8_in[0] tx_clk8_in[1] tx_clk8_in[2] tx_clk8_in[3] div by 8 or div by 4 tx_clk_in orli10g core tx1_pll (m/n) tx2_pll (x1) tx1_vcop (x m/n clock) tx_lock tx2_vcop (x 1 clock) 2.5g 2.5g 2.5g 10g 10g 10g tx_enb_in[3:0] tx1_vco tx2_vco
agere systems inc. 19 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g demultiplexer (rx) detail the demultiplexer module converts the incoming 16 bits of data at 622 mhz/850 mhz into 128 bits of data at 78 mhz/106 mhz or 64 bits of data at 156 mhz/212 mhz and sends it to the fpga logic. it has been implemented in two stages: the first stage converts each incoming bit into a byte stream and the second stage bit interleaves these bytes into 128/64 bits, depending upon the mode of operation. the low-speed clocks are generated by this block. these clocks are then driven back to this block from the low-speed clock tree network. functionally, the demultiplexer architecture consists of three blocks: the serial to parallel conversion, the counters, and the interleaving. the first stage of the line interface module (demulti- plexer) converts each incoming bit of data into a byte stream on a divided-by-8 clock. the data is first regis- tered on the rising edge of the clock input. the clock dividers also runs parallel to data shift (serial to paral- lel), on the rising edge of the input clock. an enable is created when a complete byte is taken in. this enable signal is used to register the serial-to-parallel con- verted data at the high-speed input clock. this ensures that the data can be safely transferred to the low-speed clock. this data is then transferred to the divided clock, allowing a timing margin of approximately half the divided clock period. the high-speed demultiplexer converts the incoming data as blocks of bytes. the byte boundaries of incom- ing data are unknown and are irrelevant to this module. this data is then interleaved to the 128/64 bits of out- put data, depending on the mode of operation (divide- by-4/divide-by-8). in 10g mode, the output data is assigned the retimed 128/64 bits of data from the first stage of line interface registered at the input clock [0]. in 2.5g mode, the output data is assigned four concat- enated 32/16 bits of data from the first stage of line interface registered at input clocks [0 to 3]. the inter- leaving is done at bit level because the serial-to-paral- lel converter operates on bits of incoming data. in 10g mode, it is assumed that all the incoming 16 bits of data are synchronized to the input clock [0]. this block also generates the clock enables used by the output line interface (multiplexer) module for registering the data on the high-speed clock. these enables along with the enables from other clocks are selected through the high-speed clock mux for the output line interface block.
20 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g demultiplexer (rx) detail (continued) figure 5 shows the valid data output bits from the demultiplexer in each of the four modes (divide-by-8, 10g and 2.5g modes, and divide-by-4, 10g and 2.5g modes). figure 6 ? figure 9 show the demultiplexer input data and clock waveforms and output clock, enable, and data waveforms for all four modes. 1338(f) figure 5. demultiplexer output data structure 4x4 to 32 demux or 4x4 to 16 demux rx_dat_out 16 or 32 rx_dat_out 16 or 32 rx_dat_out 16 or 32 rx_dat_out 16 or 32 rx_dat_in 16 rx_clk_in 4 128 112 96 80 64 48 32 16 0 10g 2.5g 8 mode 4 mode 2.5g 10g undefined single channel channel 3 channel 2 channel 1 channel 0
agere systems inc. 21 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g demultiplexer (rx) detail (continued) 1340(f) figure 6. demultiplexer serial-to-parallel conversion ? divide by 8, 10g mode (rx_enb8_out[1:3] = 0) 0048c1908 0 0159d3b2a 0 0 2 6 ae5 d4c 0 037bf7f6e 0 00000000 01234567 0 00000000 89abcdef 0 00000000 13579bdf 0 00000000 02468ace 0 rx_clk_in0 rx_clk8_out0 (rx_clk8_out[1:3] = 0) rx_dat_in [15:12] rx_enb8_out0 rx_dat_in [11:8] rx_dat_in [7:4] rx_dat_in [3:0] rx_dat_out [127:96] rx_dat_out [95:64] rx_dat_out [63:32] rx_dat_out [31:0]
22 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g demultiplexer (rx) detail (continued) 1341(f) figure 7. demultiplexer serial-to-parallel conversion ? divide by 4, 10g mode 0 048c19080 00000000 01234567 0 (rx_enb8_out[1:3] = 0) rx_clk_in0 rx_clk8_out0 (rx_clk8_out[1:3] = 0) rx_dat_in [15:12] rx_enb8_out0 rx_dat_in [11:8] rx_dat_in [7:4] rx_dat_in [3:0] rx_dat_out [63:32] rx_dat_out [31:0] 0159d3b2a0 026ae5d4c0 037bf7f6e0 13579bdf 00000000 89abcdef 0 02468ace
agere systems inc. 23 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g demultiplexer (rx) detail (continued) 1342(f) figure 8. demultiplexer serial-to-parallel conversion ? divide by 8, 2.5g mode 001234567 0 089abcdef 0 013579bdf 0 002468ace 0 00000000 01234567 0 00000000 89abcdef 0 00000000 13579bdf 0 00000000 02468ace 0 rx_clk_in[0:3] rx_clk8_out[0:3] rx_dat_in [15:12] rx_enb8_out[3:0] rx_dat_in [11:8] rx_dat_in [7:4] rx_dat_in [3:0] rx_dat_out [127:96] rx_dat_out [95:64] rx_dat_out [63:32] rx_dat_out [31:0]
24 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g demultiplexer (rx) detail (continued) 1343(f) figure 9. demultiplexer serial-to-parallel conversion ? divide by 4, 2.5g mode 0 0123 45670 0000 0123 0 rx_clk_in[3:0] rx_clk8_out[3:0] rx_dat_in [15:12] rx_enb8_out[3:0] rx_dat_in [11:8] rx_dat_in [7:4] rx_dat_in [3:0] rx_dat_out [111:96] rx_dat_out [79:64] 089abcdef0 013579bdf0 002468ace0 4567 0000 89ab 0 cdef 0000 1357 0 9bdf 0000 0246 0 8ace rx_dat_out [47:32] rx_dat_out [15:0]
agere systems inc. 25 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g multiplexer (tx) detail the multiplexer module converts the incoming 128 bits of data from the fpga logic at 78 mhz/106 mhz or 64 bits of data from the fpga logic at 156 mhz/212 mhz into 16 bits of data at 622 mhz/850 mhz. it has been implemented as two stages. the first stage deinterleaves each incoming byte into a different byte stream that can be serially output on the output data pins. the second stage outputs these bytes into 16 bits or four groups of 4 bits, depending upon the mode of operation. functionally, the multiplexer architecture consists of three blocks: the parallel-to-serial conversion, the counters, and the deinterleaving. for 2.5g divide-by-8 mode, the first stage of the line interface module deinterleaves each incoming byte of data into a different byte stream on the 78 mhz/106 mhz (tx_clk8_in[3:0]) clock. this data is then registered on the rising edge of the 622 mhz/850 mhz (tx_clk_in) clock at the falling edge of the 78 mhz/106 mhz clock. the enable inputs (tx_enb8_in[3:0]) are used to transfer data from the low-speed clock to the high-speed clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-speed clock. for 2.5g divide-by-4 mode, the first stage of the line interface module deinterleaves each incoming byte of data into a different byte stream on the 156 mhz/212 mhz (tx_clk8_in[3:0]) clock. this data is then registered on the rising edge of the 622 mhz/850 mhz (tx_clk_in) clock at the falling edge of the 156 mhz/212 mhz clock. the enable inputs (tx_enb8_in[3:0]) are used to transfer data from the low-speed clock to the high-speed clock, as well as synchronizing the counters of parallel-to-serial conversion which are running at the high-speed clock. in 2.5g modes, the enable inputs (tx_enb8_in[3:0]) are required to be four (divide by 4) or eight (divide by 8) tx_clk_in clock cycles wide. they have to be synchronous to their corresponding tx_clk8_in[3:0] clock. each of these four tx_clk8_in[3:0] clocks must also be frequency locked to the tx_clk_in signal. in 10g modes, the enable inputs (tx_enb8_in[3:0]) are also required to be four (divide by 4) or eight (divide by 8) tx_clk_in clock cycles wide. in 10g modes, the other enable inputs (tx_enb8_in[3:1]) are unused. unlike 2.5g modes, this enable is synchronous to a divided version of tx_clk_in from the embedded core. in 10g modes, the tx_clk8_in[3:0] inputs are not used. for version 2 orli10g devices, the enable signal can also optionally be generated automatically in the embedded core, thus removing the need to supply tx_enb8_in0 when that mode is selected. a second new option for the version 2 orli10g devices will synchronize the tx_enb8_in0 enable with the divided version of tx_clk_in in the embedded core to simplify timing. in both 2.5g and 10g modes, the tx_clk_out[3:0] clock outputs from the orli10g are provided for transferring each 4 bits of data per clock. for both 2.5g modes and 10g modes, all data to be transmitted to the embedded core must be frequency locked to the tx_clk_in signal. thus, the divided version of this clock found at the embedded core interface should always be used to transfer data from the fpga logic to the embedded core. in 2.5g modes, this same clock signal should also be used to generate the enable signals as discussed previously. these clock signals are available from the tx pll outputs (tx1_vco, tx1_vcop, tx2_vco, tx2_vcop). figure 10 shows the valid data input bits to the multiplexer in each of the four modes (divide-by-8, 10g and 2.5g modes, and divide-by-4, 10g and 2.5g modes). figure 11 ? figure 14 show the multiplexer input transmit reference clock, data, enable, and clock waveforms and output clock and data waveforms for all four modes. in version 2 of the orli10g device, additional capabilities are added to the multiplexer block. the first allows the clock inputs tx_clk8_in[3:0] to be optionally generated in the embedded core in 2.5g mode, as is done for 10g mode for version 1. the second option allows all enables tx_enb8_in[3:0] to be generated in the embedded core for both 2.5g and 10 g modes. the third option allows the enable inputs tx_enb8_in[3:0] to continue to be used, but they are re-synchronized in the embedded core before being used. all options allow for simplification of the fpga to embedded core interface. if none are selected, the orli10g defaults to version 1 compatible operation.
26 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g multiplexer (tx) detail (continued) 1339(f) figure 10. multiplexer input data structure 4x4 to 32 demux or 4x4 to 16 demux tx_dat_in 16 or 32 tx_dat_in 16 or 32 tx_dat_in 16 or 32 tx_dat_in 16 or 32 tx_dat_out 16 tx_clk_out 4 transmit reference clock tx_clk_in 128 112 96 80 64 48 32 16 0 10g 2.5g 8 mode 4 mode 2.5g 10g undefined single channel channel 3 channel 2 channel 1 channel 0
agere systems inc. 27 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g multiplexer (tx) detail (continued) 1344(f) figure 11. multiplexer parallel-to-serial conversion ? divide by 8, 10g mode 00000000 tx_clk_in tx_clk8_out[3:0] tx_dat_out [15:12] tx_dat_out [11:8] tx_dat_out [7:4] tx_dat_out [3:0] tx_dat_in [127:96] tx_dat_in [95:64] tx_dat_in [63:32] tx_dat_in [31:0] tx_enb8_in0 01234567 0 00000000 89abcdef 0 00000000 13579bdf 0 00000000 02468ace 0 048c1908 0 0 159d3b2a 0 0 26ae5d4c 0 0 37bf7f6e 0 0
28 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g multiplexer (tx) detail (continued) 1345(f) figure 12. multiplexer parallel-to-serial conversion ? divide by 4, 10g mode tx_clk_in tx_clk_out[3:0] tx_dat_in [63:32] tx_dat_in [31:0] tx_enb8_in0 13579bdf 048c19080 0 159d3b2a0 0 26ae5d4c0 0 37bf7f6e0 0 00000000 01234567 0 02468ace 00000000 89abcdef 0 tx_dat_out [15:12] tx_dat_out [11:8] tx_dat_out [3:0] tx_dat_out [7:4]
agere systems inc. 29 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g multiplexer (tx) detail (continued) 1346(f) figure 13. multiplexer parallel-to-serial conversion ? divide by 8, 2.5g mode 00000000 tx_clk_in tx_clk8_out[3:0] tx_dat_out [15:12] tx_dat_out [11:8] tx_dat_out [7:4] tx_dat_out [3:0] tx_dat_in [127:96] tx_dat_in [95:64] tx_dat_in [63:32] tx_dat_in [31:0] tx_clk8_in[3:0] tx_enb8_in[3:0] 01234567 0 00000000 89abcdef 0 00000000 13579bdf 0 00000000 02468ace 0 01234567 0 0 89abcdef 0 0 13579bdf 0 0 02468ace 0 0
30 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g multiplexer (tx) detail (continued) 1347(f) figure 14. multiplexer parallel-to-serial conversion ? divide by 4, 2.5g mode tx_clk_in tx_clk_out[3:0] tx_dat_in [111:96] tx_dat_in [79:64] tx_clk8_in[3:0] tx_enb8_in[3:0] 4567 012345670 0 89abcdef0 0 13579bdf0 0 02468ace0 0 0000 0123 0 tx_dat_in [47:32] tx_dat_in [15:0] tx_dat_out [31:0] tx_dat_out [63:32] cdef 0000 89ab 0 9bdf 0000 1357 0 8ace 0000 0246 0 tx_dat_out [63:32] tx_dat_out [31:0]
agere systems inc. 31 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g embedded plls the orli10g embedded (transmit and receive) plls are based on the 4e series fpga high-speed programma- ble pll (hppll). the 4e pll consists of a phase/frequency detector (pfd), a charge pump/filter, a multitap volt- age controlled oscillator (vco), a duty cycle synthesis circuitry, a power regulator, two programmable dividers, phase shift selector multiplexers, a lock signal generator, and a current dac. a block diagram of the programma- ble pll is shown in figure 15. the receive path rx1_pll and transmit path tx1_pll, which can be programmed to create a n/m frequency clock, are based on this design. the receive path rx2_pll and transmit path tx2_pll create a x1 clock. this is essentially the same pll without the m and n divider. the rcki input to the plls comes from an input clock to the orli10g that has been divided in frequency by either 4 or 8 (programmable). as shown in figure 3, rx1_pll and rx2_pll are driven by the divided version of rx_clk_in0. as shown in figure 4, tx1_pll and tx2_pll are driven by the divided versions of tx_clk_in. it should be noted that the speed of the orli10g line interface is therefore either 4x or 8x the operating speed of the embedded plls. the clock feedback loops for the rx2_pll and tx2_pll should be routed from the clock network in the fpga core so as to compensate for the routing delays to the fpga logic interface. the source to the tx2_fbcki or rx2_fbcki inputs must come from an fpga clock network driven by the vco output (otherwise any phase shift- ing on vcop is removed by the feedback loops). in this way, the clock skew at the embedded core/fpga logic boundary is zero for the receive and transmit plls. all plls include a phase shift selector which allows phase shift adjustments of each clock in increments of 1/8 the period of the clock. this phase shifted output is available on the vcop output of the pll. all functions of the embedded core plls are user controlled through a gui provided with the orli10g design kit software. 1331(f) figure 15. orli10g programmable pll block diagram rcki m<5:0> n<5:0> sel<2:0> bypass m divider n divider pfd lock generator charge pump and filter vco phase select rcko lock vcop vco tx2_fbcki rx2_fbcki
32 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s orli10g embedded programmable plls specifications table 2. programmable pll specifications notes: multiplication and division values can both be used on one pll output (example 3/4x). for more information, see the series 4 pll application note. orli10g reset requirements both the embedded core portion and the fpga portion are reset at powerup. the embedded core is also reset, as shown in table 3, based on other conditions. for version 1 orli10g devices, these resets are all asynchronous and must be held in reset for at least 8 ns. for version 2, the resets can also optionally be set to be asynchronous on with synchronous release. table 3 also shows the conditions upon which the i/o are 3-stated. table 3. orli10g reset requirements typically, the following reset sequence should be followed for the orli10g: place the device in reset by driving reset_tx = 1, reset_rx = 1, and by placing the fpga portion into reset. release the embedded core from reset by driving reset_tx = 0 and reset_rx = 0. release the fpga portion from reset. parameters min nom max unit v dd 15 1.425 1.5 1.575 v v dd 33 3.0 3.3 3.6 v operating temperature ? 40 ? 125 c input clock frequency 60 ? 420 mhz input duty cycle 30 ? 70 % input clock jitter requirement ?? tbd uip-p input jitter transfer ?? tbd uip-p output clock frequency 60 ? 420 mhz output duty cycle 45 50 55 % dc power consumption ? 50 ? mw total on current (dc) ? 14 ? ma total off current (dc) ? 30.0 ? pa cycle to cycle jitter (p-p) ? <0.02 tbd uip-p period jitter (p-p) tbd tbd tbd uip-p duty cycle jitter (p-p) tbd tbd tbd uip-p vco output vs. vcop output jitter ?? tbd ps lock time ? <50 ? s frequency multiplication (tx1_pll and rx1_pll) 2x, 3x, 4x, 5x, 6x, 7x, 8x ? frequency division (tx1_pll and rx1_pll) 1/8x, 1/7x, 1/6x, 1/5x, 1/4x, 1/3x, 1/2x ? duty cycle adjust of output clock(s) 12.5, 25, 37.5, 50, 62.5, 75, 87.5 % delay adjust of output clock 0, 45, 90, 135, 180, 225, 270, 315 degrees phase shift between vco and vcop 0, 45, 90, 135, 180, 225, 270, 315 degrees condition tx mux block tx pll rx demux block rx pll embedded i/o powerup reset reset reset reset 3-state fpga configuration reset reset reset reset active ts_all pin = 1 ?? ? ? 3-state reset_tx pin = 1 reset reset ?? active reset_rx pin = 1 ?? reset reset active pwron pin = 1 ? powerdown ? powerdown active
agere systems inc. 33 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s line interface circuit specifications power supply decoupling lc circuit the 622 mhz ? 850 mhz line interface macro contains both analog and digital circuitry. the line interface function, for example, is implemented as primarily a digital function, but it relies on a conventional analog phase-locked loop to provide its divided clocks. the internal analog phase-locked loop contains a voltage-controlled oscillator. this circuit will be sensitive to digital noise generated from the rapid switching transients associated with internal logic gates and parasitic inductive elements. generated noise that contains frequency components beyond the band- width of the internal phase-locked loop (about 3 mhz) will not be attenuated by the phase-locked loop and will impact bit error rate directly. thus, separate power supply pins are provided for these critical analog circuit ele- ments. additional power supply filtering in the form of an lc pi filter section will be used between the power supply source and these device pins as shown in figure 16. the corner frequency of the lc filter is chosen based on the power supply switching frequency, which is between 100 khz and 300 khz in most applications. capacitors c1 and c2 are large electrolytic capacitors to provide the basic cutoff frequency of the lc filter. for example, the cutoff frequency of the combination of these elements might fall between 5 khz and 50 khz. capaci- tor c3 is a smaller ceramic capacitor designed to provide a low-impedance path for a wide range of high-frequency signals at the analog power supply pins of the device. the physical location of capacitor c3 must be as close to the device lead as possible. multiple instances of capacitors c3 can be used if necessary. the recommended filter for the hsi macro is shown below: l = 4.7 h, rl = 1 ? , c1 = 0.01 f, c 2 = 0 . 0 1 f, c 3 = 4 . 7 f. 5-9344(f).a figure 16. sample power supply filter network for analog li power supply pins c2 + c3 + to device v dd 33, v dd 33_a[7:4] v ss , v ss 33_a[7:4] c1 + from power supply source l
34 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s xgmii orca 4e receive analysis xgmii considerations the stringent 10 gbit media independent interface specifications from the ieee 802.3ae standards are met in the fpga side of the orli10g device. figure 17 and table 4 show a simplified block diagram for this interface and the receive voltage levels for the hstl inputs to the orli10g device. further details are available in the series 4 i/o application note. the orli10g device meets the 480 ps input setup time and 480 ps input hold time requirements for the xgmii receiver inputs into the fpga side of the fpsc with the embedded io ddr cells on the fpga side of the fpsc. the plls are not used on input due to this being a forward clocked interface. the orli10g meets the clock-to-out specification on the xgmii ddr outputs by using the output shift register to produce a nonduty cycle-dependent output. an embedded output ddr capability is also available. the output clock is then centered around this data eye using internal plls. there are two considerations to note about the pinout location of the xgmii input clocks: 1. the xgmii input clocks must be located at the c pad of the programmable i/o cells (pics). in the pinout tables, the pads are labeled on a pin-by-pin basis. for example, a pin whose pad is referenced as pl1c can be used as an xgmii input clock, but pins referenced as pl1a, pl1b, or pl1d cannot be used as an xgmii input clock. 2. the xgmii input data pins can be no further then six pics away from the xgmii input clock pin. this means that in the 416 pbga package, the clock needs to be driven on two pins to be able to clock in the 32-bit xgmii input data bus. due to the strict pinout locations mentioned above, when implementing a xgmii interface, the microprocessor interface (mpi) will not be available in the 416 pbga package. 1550.a(f) figure 17. simplified xgmii block diagram hstl clock clock v ddio v dd15 v ddio = 1.5 v nom hstl v ddio = 1.5 v nom v ref v ddio 2 ddr data ddr data customer device orli10g system interface line interface
agere systems inc. 35 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s xgmii orca 4e receive analysis (continued) table 4. hstl input requirements to fpga absolute maximum ratings stresses in excess of the absolute maximum ratings can cause permanent damage to the device. these are abso- lute stress ratings only. functional operation of the device is not implied at these or any other conditions in excess of those given in the operations sections of this data sheet. exposure to absolute maximum ratings for extended periods can adversely affect device reliability. the orca series 4 fpscs include circuitry designed to protect the chips from damaging substrate injection cur- rents and to prevent accumulations of static charge. nevertheless, conventional precautions should be observed during storage, handling, and use to avoid exposure to excessive electrical stress. table 5. absolute maximum ratings recommended operating conditions table 6. recommended operating conditions notes: the maximum recommended junction temperature (t j ) during operation is 125 c. timing parameters in this data sheet and orca foundry are characterized under tighter voltage and temperature conditions than t he recommended operating conditions in this table. the internal plls operate from the v dd 33 and v dd 33_a power supplies. these power supplies should be well isolated from all other power supplies on the board for proper operation. inputs low nom high v ddio 1.4 v 1.5 v 1.6 v v ih (min level) 0.88 v 0.95 v 1.10 v v ref 0.68 v 0.75 v 0.90 v v il (max level) 0.48 v 0.55 v 0.70 v parameter symbol min max unit storage temperature t stg ? 65 150 c power supply voltage with respect to ground v dd 33 ? 0.3 4.2 v v ddio ? 0.3 4.2 v v dd 33, v dd 33_a ? 0.3 2.0 v v dd 15 ? 0.3 2.0 v input signal with respect to ground v in ? 0.3 v ddio + 0.3 v signal applied to high-impedance output ?? 0.3 v ddio + 0.3 v maximum package body temperature ?? 220 c parameter symbol min max unit power supply voltage with respect to ground v dd 33 2.7 3.6 v v ddio 1.4 3.6 v v dd 33, v dd 33_a 1.4 1.6 v v dd 15 1.4 1.6 v input voltages v in ? 0.3 v ddio + 0.3 v junction temperature t j ? 40 125 c
36 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s embedded core lvds i/o table 7. driver dc data* *v dd 33 = 3.1 v ? 3.5 v, v dd 15 = 1.4 v ? 1.6 v, ? 40 c, and slow-fast process. ? external reference, ref10 = 1.0 v 3%, ref14 = 1.4 v 3%. table 8. driver ac data * *v dd 33 = 3.1 v ? 3.5 v, v dd 15 = 1.4 v ? 1.6 v, ? 40 c, and slow-fast process. table 9. driver power consumption * *v dd 33 = 3.1 v ? 3.5 v, v dd 15 = 1.4 v ? 1.6 v, ? 40 c, and slow-fast process. parameter symbol test conditions min typ max unit output voltage high, v oa or v ob v oh r load = 100 ? 1% ?? 1.475 ? v output voltage low, v oa or v ob v ol r load = 100 ? 1% 0.925 ? ?? v output differential voltage ? v od ? r load = 100 ? 1% 0.25 ? 0.45 ? v output offset voltage v os r load = 100 ? 1% 1.125* ? 1.275 ? v output impedance, differential r o v cm = 1.0 v and 1.4 v 80 100 120 ? r o mismatch between a and b ? r o v cm = 1.0 v and 1.4 v ?? 10 % change in differential voltage between complementary states ?? v od ? r load = 100 ? 1% ?? 25 mv change in output offset voltage between complementary states ? v os r load = 100 ? 1% ?? 25 mv output current i sa, i sb driver shorted to gnd ?? 24 ma output current i sab drivers shorted together ?? 12 ma power-off output leakage |ixa|, |ixb| v dd = 0 v v pad , v padn = 0 v ? 2.5 v ?? 10 ma parameter symbol test conditions min max unit v od fall time, 80% to 20% t f z l = 100 ? 1% c pad = 3.0 pf, c pad = 3.0 pf 100 210 ps v od rise time, 20% to 80% t r z l = 100 ? 1% c pad = 3.0 pf, c pad = 3.0 pf 100 210 ps differential skew: |t phla ? t plhb | or |t phlb ? t plha | t skew1 any differential pair on package at 50% point of the transition ? 50 ps channel-to-channel skew: |tpdiffm ? tpdiffn| t skew2 any two signals on package at 0 v differential ?? ps propagation delay time t plh t phl z l = 100 ? 1% c pad = 3.0 pf, c padn = 3.0 pf 0.54 0.55 1.10 1.09 ns ns parameter symbol test conditions min max unit driver dc power pd dc z l = 100 ? 1% ? 26.0 mw driver ac power pd ac z l = 100 ? 1% c pad = 3.0 pf, c padn = 3.0 pf ? 64 w/mhz
agere systems inc. 37 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s embedded core lvds i/o (continued) lvds receiver buffer requirements table 10. receiver ac data * *v dd = 3.1 v ? 3.5 v, 0 c ? 125 c, slow-fast process. table 11. receiver power consumption* *v dd = 3.1 v ? 3.5 v, 0 c ? 125 c, slow-fast process. table 12. receiver dc data * *v dd = 3.1 v ? 3.5 v, 0 c ? 125 c, slow-fast process. ? external reference, ref10 = 1.0 v 3%, ref14 = 1.4 v 3%. table 13. lvds operating parameters note: under worst-case operating condition, the lvds driver will withstand a disabled or unpowered receiver for an unlimited per iod of time without being damaged. similarly, when outputs are short-circuited to each other or to ground, the lvds will not suffer permane nt dam- age. the lvds driver supports hot insertion. under a well-controlled environment, the lvds i/o can drive backplane as well as c able. parameter symbol test conditions min max unit pulse-width distortion t pwd v idth = 100 mv, 311 mhz ? 160 ps propagation delay time t plh t phl c l = 0.5 pf 0.60 0.60 1.42 1.47 ns ns with common-mode variation (0 v to 2.4 v) ?? t pd ? c l = 0.5 pf ? 50 ps output rise time, 20% to 80% t r c l = 0.5 pf 150 350 ps output fall time, 80% to 20% t f c l = 0.5 pf 150 350 ps parameter symbol test conditions min max unit receiver dc power p rdc dc ? 20.4 mw receiver ac power p rac ac c l = 1.5 pf ? 4.5 w/mhz parameter symbol test conditions min typ max unit input voltage range, via or vib v i ? v gpd ? < 925 mv dc ? 1 mhz 0.0 1.2 2.4 v input differential threshold v idth ? v gpd ? < 925 mv 400 mhz ? 100 ? 100 mv input differential hysteresis v hyst (+v idthh ) ? ( ? v idthl ) ??? ? mv receiver differential input impedance r in with build-in termination, center-tapped 80 100 120 ? parameter test conditions min normal max unit transmit termination resistor ? 80 100 120 ? receiver termination resistor ? 80 100 120 ? temperature range ?? 40 ? 125 c power supply v dd 33 ? 3.1 ? 3.5 v power supply v dd 15 ? 1.4 ? 1.6 v power supply v ss ?? 0 ? v
38 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s timing characteristics receive input data interface receive sts-48/sts-192 (2.5g/10g) data inputs figure 18 illustrates the timing for the receive sts-48/sts-192 data stream. both the clock and data pins are low- voltage differential signal (lvds) input buffers. the expected clock rate is 622 mhz ? 850 mhz, and the receive data is clocked on the rising edge of the clock. in 2.5g mode, each of the four channels uses one set of rx_clk_inn and 4 rx_dat_inn data pins. in 10g mode, only rx_clk_in0 is used, along with the rx_dat_in[15:0] pins. 5-9085.b (f) figure 18. receive input data timing table 14. receive data input timing it is recommended that the rx clock be inverted by crossing the lvds pin pair, that is, connect the n to the p and the p to the n. this is because the embedded li requires the rx data to be centered on the rx clock, and typically the devices that drive the orli10g transmit clock and data on the same clock edge. the timing values for the diagram are given in table 14. symbol parameter ? 1 ? 2 ? 3unit min max min max min max t1 clock frequency ? 667 ? 790 ? 850 mhz t2 data setup time required 300 ? 225 ? 210 ? ps t3 data hold time required 300 ? 225 ? 210 ? ps rx_clk_in_[3:0] rx_data_in_[15:0] p n p n t1 t3 t2
agere systems inc. 39 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s timing characteristics (continued) transmit sts-48/sts-192 (2.5g/10g) data outputs figure 19 illustrates the timing for the transmit sts-48/sts-192 data stream. both the clock and data pins are driven with low-voltage differential signal (lvds) output buffers. the expected clock rate is 622 mhz ? 850 mhz and the transmit data is clocked out on the rising edge of the clock. in 2.5g mode, each of the four channels uses one set of tx_clk_outn with four tx_dat_outn data pins. in 10g mode, only tx_clk_out[0] is used with the 16 tx_dat_out[15:0] pins. the timing values for the diagram are given in table 15. 5-9089.c(f) figure 19. transmit output data timing table 15. transmit data output timing * this requirement is for all sources of the output clocks (e.g., rclksi, etc.). it is recommended that the tx clock be inverted by crossing the lvds pin pair, that is, connect the n to the p and the p to the n. this is because the receiving device that will be driven by the orli10g typically requires that data be centered around the clock, but the orli10g drives both the clock and data from the same clock edge. symbol parameter ? 1 ? 2 ? 3unit min max min max min max t4 clock frequency ? 667 ? 790 ? 850 mhz ? duty cycle 455545554555% t5 data delay from clock edge ? 300 300 ? 225 225 ? 210 210 ps t6 data rise time: 20% ? 80% 100 200 100 200 100 200 ps t7 data fall time: 80% ? 20% 100 200 100 200 100 200 ps t5 tx_dat_out[15:0] p n p n t6 t7 tx_clk_out[3:0] t4
40 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s input/output buffer measurement conditions (non-lvds buffer) note: switch to v dd for t plz /t pzl ; switch to gnd for t phz /t pzh . 5-3234(f) figure 20. ac test loads 5-3233.a(f) figure 21. output buffer delays 5-3235(f) figure 22. input buffer delays 50 pf a. load used to measure propagation delay to the output under test to the output under test 50 pf v cc gnd 1 k ? b. load used to measure rising/falling edges v dd t phh v dd /2 v ss out[i] pad out 1.5 v 0.0 v t pll pad out[i] ac test loads (shown above) ts[i] out 0.0 v 1.5 v t phh t pll pad in[i] in 3.0 v v ss v dd /2 v dd pad in in[i]
agere systems inc. 41 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s lvds buffer characteristics termination resistor the lvds drivers and receivers operate on a 100 ? differential impedance, as shown below. external resistors are not required. the differential driver and receiver buffers include termination resistors inside the device package, as shown in figure 23. 5-8703(f) figure 23. lvds driver and receiver and associated internal components lvds driver buffer capabilities under worst-case operating condition, the lvds driver must withstand a disabled or unpowered receiver for an unlimited period of time without being damaged. similarly, when its outputs are short-circuited to each other or to ground, the lvds driver will not suffer permanent damage. figure 24 illustrates the terms associated with lvds driver and receiver pairs. 5-8704(f) figure 24. lvds driver and receiver 5-8705(f) figure 25. lvds driver lvds driver 50 ? 50 ? lvds receiver center tap device pins 100 ? external v gpd v oa v ob v ia v ib a b aa bb driver interconnect receiver v oa a v ob b c a c b r load v od = (v oa ? v ob ) v
42 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information this section describes the pins and signals that perform fpga-related functions. during configuration, the user- programmable i/os are 3-stated and pulled up with an internal resistor. if any fpga function pin is not used (or not bonded to package pin), it is also 3-stated and pulled up after configuration. table 16. fpga common-function pin description symbol i/o description dedicated pins v dd 33 ? 3 v positive power supply. v dd 15 ? 1.5 v positive power supply for internal logic. v ddio ? positive power supply used by i/o banks. gnd ? ground supply. ptemp i temperature-sensing diode pin. dedicated input. reset i during configuration, reset forces the restart of configuration and a pull-up is enabled. after configuration, reset can be used as a general fpga input or as a direct input, which causes all plc latches/ffs to be asynchronously set/reset. cclk i o in the master and asynchronous peripheral modes, cclk is an output which strobes con- figuration data in. in the slave or readback after configuration, cclk is input synchronous with the data on din or d[7:0]. cclk is an output for daisy-chain operation when the lead device is in master, peripheral, or system bus modes. done i as an input, a low level on done delays fpga start-up after configuration.* o as an active-high, open-drain output, a high level on this signal indicates that configura- tion is complete. done has an optional pull-up resistor. prgm i prgm is an active-low input that forces the restart of configuration and resets the bound- ary-scan circuitry. this pin always has an active pull-up. rd_cfg i this pin must be held high during device initialization until the init pin goes high. this pin always has an active pull-up. during configuration, rd_cfg is an active-low input that activates the ts_all function and 3-states all of the i/o. after configuration, rd_cfg can be selected (via a bit stream option) to activate the ts_all function as described above, or, if readback is enabled via a bit stream option, a high-to-low transition on rd_cfg will initiate readback of the configuration data, including pfu output states, starting with frame address 0. rd_data/tdo o rd_data/tdo is a dual-function pin. if used for readback, rd_data provides configu- ration data out. if used in boundary-scan, tdo is test data out. cfg_irq /mpi_irq o during jtag, slave, master, and asynchronous peripheral configuration assertion on this cfg_irq (active-low) indicates an error or errors for block ram or fpsc initialization. mpi active-low interrupt request output. * the fpga states of operation section in the orca series 4 data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con- figuration pins (and the activation of all user i/os) is controlled by a second set of options.
agere systems inc. 43 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information (continued) figure 16. fpga common-function pin description (continued) symbol i/o description special-purpose pins (can also be used as a general i/o.) m[3:0] i during powerup and initialization, m0 ? m3 are used to select the configuration mode with their values latched on the rising edge of init . during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o.* pll_ck[0:1,6:7] i/o dedicated pcm clock pins. these pins are a user-programmable i/o pins if not used by plls. p[tblr]clk[1:0] [tc] i/o pins dedicated for the primary clock. these are input pins on the middle of each side with differential pairing. they may be used as general i/o pins if not needed for clocking pur- poses. tdi, tck, tms i if boundary-scan is used, these pins are test data in, test clock, and test mode select inputs. if boundary-scan is not selected, all boundary-scan functions are inhibited once con- figuration is complete. even if boundary-scan is not used, either tck or tms must be held at logic 1 during configuration. each pin has a pull-up enabled during configuration. i/o after configuration, these pins are user-programmable i/o.* rdy/busy /rclk o during configuration in peripheral mode, rdy/rclk indicates another byte can be written to the fpga. if a read operation is done when the device is selected, the same status is also available on d7 in asynchronous peripheral mode. after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* i/o during the master parallel configuration mode, rclk is a read output signal to an external memory. this output is not normally used. hdc o high during configuration is output high until configuration is complete. it is used as a con- trol output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* ldc o low during configuration is output low until configuration is complete. it is used as a control output, indicating that configuration is not complete. i/o after configuration, this pin is a user-programmable i/o pin.* init i/o init is a bidirectional signal before and during configuration. during configuration, a pull-up is enabled, but an external pull-up resistor is recommended. as an active-low, open-drain output, init is held low during power stabilization and internal clearing of memory. as an active-low input, init holds the fpga in the wait-state before the start of configuration. after configuration, this pin is a user-programmable i/o pin.* cs0 , cs1 ics0 and cs1 are used in the asynchronous peripheral, slave parallel, and microproces- sor configuration modes. the fpga is selected when cs0 is low and cs1 is high. during configuration, a pull-up is enabled. i/o after configuration, these pins are user-programmable i/o pins.* rd /mpi_strb ird is used in the asynchronous peripheral configuration mode. a low on rd changes d7 into a status output. as a status indication, a high indicates ready, and a low indicates busy. wr and rd should not be used simultaneously. if they are, the write strobe over- rides. this pin is also used as the mpi data transfer strobe. i/o after configuration, if the mpi is not used, this pin is a user-programmable i/o pin.* * the fpga states of operation section in the orca series 4 data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con- figuration pins (and the activation of all user i/os) is controlled by a second set of options.
44 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information (continued) figure 16. fpga common-function pin description (continued) symbol i/o description a[17:0] mpi_burst mpi_bdip mpi_tsz[1:0] a[21:0] i during mpi mode, the a[17:0] are used as the address bus driven by the powerpc bus master utilizing the least significant bits of the powerpc 32-bit address. o during master parallel configuration mode, a[17:0] address the configuration eprom. in mpi mode, many of the a[n] pins have alternate uses as described below. see the special function blocks section for more mpi information. during configuration, if not in master par- allel or an mpi configuration mode, these pins are 3-stated with a pull-up enabled. a[21] is used as the mpi_burst . it is driven low to indicate a burst transfer is in progress. driven high indicates that the current transfer is not a burst. a[20] is used as the mpi_bdip . it is driven by the powerpc processor; assertion of this pin indicates that the second beat in front of the current one is requested by the master. negated before the burst transfer ends to abort the burst data phase. a[19:18] are used as the mpi_tsz[1:0] signals and are driven by the bus master to indicate the data transfer size for the transaction. set 01 for byte, 10 for half-word, and 00 for word. during master parallel mode a[21:0], address the configuration eproms up to 4 mbytes. if not used for mpi, these pins are user-programmable i/o pins.* mpi_ack oin powerpc mode mpi operation, this is driven low indicating the mpi received the data on the write cycle or returned data on a read cycle. mpi_clk i this is the powerpc synchronous, positive-edge bus clock used for the mpi interface. it can be a source of the clock for the embedded system bus. if mpi is used, this can be the amba bus clock. mpi_tea o a low on the mpi transfer error acknowledge indicates that the mpi detects a bus error on the internal system bus for the current transaction. mpi_rtry o this pin requests the mpc860 to relinquish the bus and retry the cycle. d[31:0] i/o selectable data bus width from 8-, 16-, 32-bit. driven by the bus master in a write transac- tion. driven by mpi in a read transaction. i d[7:0] receive configuration data during master parallel, peripheral, and slave parallel con- figuration modes and each pin has a pull-up enabled. during serial configuration modes, d0 is the din input. d[7:3] output internal status for asynchronous peripheral mode when rd is low. after configuration, the pins are user-programmable i/o pins.* dp[3:0] i/o selectable parity bus width from 1, 2, 4-bit, dp[0] for d[7:0], dp[1] for d[15:8], dp[2] for d[23:16], and dp[3] for d[32:24]. after configuration, this pin is a user-programmable i/o pin.* din i during slave serial or master serial configuration modes, din accepts serial configuration data synchronous with cclk. during parallel configuration modes, din is the d0 input. during configuration, a pull-up is enabled. i/o after configuration, this pin is a user-programmable i/o pin.* dout o during configuration, dout is the serial data output that can drive the din of daisy-chained slave devices. data out on dout changes on the rising edge of cclk. i/o after configuration, dout is a user-programmable i/o pin.* * the fpga states of operation section in the orca series 4 data sheet contains more information on how to control these signals during start-up. the timing of done release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con- figuration pins (and the activation of all user i/os) is controlled by a second set of options.
agere systems inc. 45 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information (continued) this table describes the i/o signal ports on the embedded core portion of the device. table 17. fpsc function pin description symbol i/o description control and global pins pll_bypass i 3.3 v active-high. enables the bypass mode for both receive and both transmit plls. pwrdn i 3.3 v active-high. power down all lvds links and both receive and both transmit plls. reset_rx i 3.3 v active-high. resets the receive plls and the demultiplexer block. reset_tx i 3.3 v active-high. resets the transmit plls and the multiplexer block. receive i/o pins rx_dat_in_n<15:0> i lvds data input for receive side. rx_dat_in_p<15:0> i lvds data input for receive side. rx_clk_in_n<3:0> i lvds clock inputs for receive side. rx_clk_in_p<3:0> i lvds clock inputs for receive side. transmit i/o pins tx_dat_out_n<15:0> o lvds data outputs on transmit side. tx_dat_out_n<15:0> o lvds data outputs on transmit side. tx_clk_out_n<3:0> o lvds clock outputs on transmit side. tx_clk_out_n<3:0> o lvds clock outputs on transmit side. tx_clk_in_n i lvds transmit reference clock input. tx_clk_in_p i lvds transmit reference clock input. lvds input reference pins lv_ref10 ? lvds reference voltage: 1.0 v 3%. lv_ref14 ? lvds reference voltage: 1.4 v 3%. lv_reshi ? lvds resistor high pin (use 100 ? to lv_reslo pin). lv_reslo ? lvds resistor low pin (use 100 ? to lv_reshi pin). lvctap_[6:1] ? lvds input centertap (use 0.01 f to gnd).
46 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information (continued) in figure 18, an output refers to a signal flowing into the fgpa logic (out of the embedded core) and an input refers to a signal flowing out of the fpga logic (into the embedded core). table 18. embedded core/fpga interface signal description pin name i/o description receive signals rx_dat_out<127:0> o data from demultiplexer on receive side. rx_clk8_out<3:0> o divided down clocks on receive side. rx_enb8_out<3:0> o data enables on receive side. rx1_vcop o rx1_pll output clock on receive side (m/n clock) after phase select. rx1_vco o rx1_pll output clock on receive side (m/n clock) before phase select. rx2_vcop o rx2_pll output clock on receive side (x1 clock) after phase select. rx2_vco o rx2_pll output clock on receive side (x1 clock) before phase select. rx2_fbcki i pll feedback input to rx2_pll. this allows for the removal of the fpga clock routing delay. rx1_bypass i set to 1 to bypass the rx1 pll. rx2_bypass i set to 1 to bypass the rx2 pll. rx_lock o lock signal for rx1_pll and rx2_pll. this signal is a logical or of the lock signal from both plls. it is not integrated; thus, small glitches can occur on this signal during normal pll operation. transmit signals tx_dat_in<127:0> i data to multiplexer on transmit side. tx_clk8_in<3:0> i clocks to multiplexer on transmit side. tx_enb8_in[3:0] i data enables on transmit side. tx1_vcop o tx1_pll output clock on transmit side (m/n clock) after phase select. tx1_vco o tx1_pll output clock on transmit side (m/n clock) before phase select. tx2_vcop o tx2_pll output clock on transmit side (x1 clock) after phase select. tx2_vco o tx2_pll output clock on transmit side (x1 clock) before phase select. tx2_fbcki i pll feedback input to tx2 pll. this allows for the removal of the fpga clock routing delay. tx1_bypass i set to 1 to bypass the tx1 pll. tx2_bypass i set to 1 to bypass the tx2 pll. tx_lock o lock signal for tx1_pll and tx2_pll. this signal is a logical or of the lock signal from both plls. it is not integrated; thus, small glitches can occur on this signal during normal pll operation. vss_a<7:4> ? analog ground for the embedded line interface plls. v dd 33_a<7:4> ? analog power supply for the embedded line interface plls.
agere systems inc. 47 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information (continued) package pinouts table 14 provides the number of user programmable i/os available for each available package. table 20 provides the package pin and pin function for the orli10g fpsc and packages. the bond pad name is identified in the pio nomenclature used in the orca foundry design editor. the bank column provides information as to which output voltage level bank the given pin is in. the group column provides information as to the group of pins the given pin is in. this is used to show which v ref pin is used to provide the reference voltage for single-ended limited-swing i/os. if none of these buffer types (such as sstl, gtl, hstl) are used in a given group, then the v ref pin is available as an i/o pin. when the number of fpga bond pads exceeds the number of package pins, bond pads are unused. when the number of package pins exceeds the number of bond pads, package pins are left unconnected (no connects). when a package pin is to be left as a no connect for a specific die, it is indicated as a note in the device column for the fpga. the tables provide no information on unused pads. table 19. orca programmable i/os summary it is very important to note the pinout limitations for 10 gbits/s ethernet applications. specifically, the very stringent timing requirements of the xgmii specification coupled with the i/o availability and locations in the 416-pin pbga requires that the xgmii output pins be located on three sides of the device. this may cause issues with routing the xgmii bus at a board level since the xgmii specification for routing this bus on a board is only 2 in. in addition, the built-in microprocessor interface (mpi) cannot be fully utilized in the 416-pin pbga and the 680-pin pbga packages because the implementation of the xgmii interface limits the number of available address and data pins. as shown in the pair columns in table 20, differential pairs and physical locations are numbered within each bank (e.g., l19c_a0 is the nineteenth pair in an associated bank). a c indicates complementary differential whereas a t indicates true differential. an _a0 indicates the physical location of adjacent balls in either the horizontal or verti- cal direction. other physical indicators are as follows: _a1 indicates one ball between pairs. _a2 indicates two balls between pairs. _d0 indicates balls are diagonally adjacent. _d1 indicates balls are diagonally adjacent separated by one physical ball. v ref pins, shown in the pin description column in table 20, are associated to the bank and group (e.g., v ref _tl_01 is the v ref for group one of the top left (tl) bank). device 416 pbgam 680 pbgam user programmable i/o 192 316 available programmable differential pair pins 184 272 fpga configuration pins 7 7 fpga dedicated function pins 2 2 core function pins 86 86 v dd 15 28 84 v dd 33_a 4 4 v dd 33 14 28 v dd io 21 44 v ss 48 95 v ss _a 4 4 lvctap for dedicated differential channels 6 6 core lv_ref pins 4 4 total package pins 416 680
48 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s pin information (continued) table 20. pbga pinout table bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair a2 a1 ?? vss vss ??? d4 e5 ?? v dd 33 v dd 33 ??? d3 e4 ?? o prd_data rd_data/tdo ?? a1 ??? v dd 15 v dd 15 ??? c1 c1 ?? i preset_n reset_n ?? e4 d1 ?? i prd_cfg_n rd_cfg_n ?? f4 e2 ?? i pprgrm_n prgrm_n ?? c2 a2 0 (tl) ? v dd io0 v dd io0 ??? d2 f4 0 (tl) 7 i/o pl2d pll_ck0c/hppll l14c_d0 l21c_a0 e3 f3 0 (tl) 7 i/o pl2c pll_ck0t/hppll l14t_d0 l21t_a0 ? a3 0 (tl) ? v dd io0 v dd io0 ??? ? g5 0 (tl) 7 i/o pl3d ?? l22c_a0 d1 f5 0 (tl) 7 i/o pl3c vref_0_07 ? l22t_a0 a25 a18 ?? vss vss ??? e2 g4 0 (tl) 7 i/o pl4d d5 l15c_d0 l23c_d1 f3 f2 0 (tl) 7 i/o pl4c d6 l15t_d0 l23t_d1 ? b1 0 (tl) ? v dd io0 v dd io0 ??? ? h5 0 (tl) 8 i/o pl4b ?? l24c_d1 ? g3 0 (tl) 8 i/o pl4a vref_0_08 ? l24t_d1 e1 f1 0 (tl) 8 i/o pl5d hdc l16c_d0 l25c_a0 f2 g2 0 (tl) 8 i/o pl5c ldc_n l16t_d0 l25t_a0 b1 a33 ?? vss vss ??? ? h4 0 (tl) 8 i/o pl5b ?? l26c_a0 ? j5 0 (tl) 8 i/o pl5a ?? l26t_a0 g4 h3 0 (tl) 9 i/o pl6d testcfg l17c_a0 l27c_d1 h4 g1 0 (tl) 9 i/o pl6c d7 l17t_a0 l27t_d1 g3 b3 0 (tl) ? v dd io0 v dd io0 ??? f1 j4 0 (tl) 9 i/o pl7d vref_0_09 l18c_d0 l28c_d1 g2 h2 0 (tl) 9 i/o pl7c a17/ppc_a31 l18t_d0 l28t_d1 ? a34 ?? vss vss ??? h2 k5 0 (tl) 9 i/o pl8d cs0_n l19c_a0 l29c_d1 h3 j3 0 (tl) 9 i/o pl8c cs1 l19t_a0 l29t_d1 ? c2 0 (tl) ? v dd io0 v dd io0 ??? g1 h1 0 (tl) 10 i/o pl9d ? l20c_a0 l30c_a0 h1 j2 0 (tl) 10 i/o pl9c ? l20t_a0 l30t_a0 ? b2 ?? vss vss ??? ? k4 0 (tl) 10 i/o pl9a ??? j4 l5 0 (tl) 10 i/o pl10d init_n l21c_a0 l31c_d1 k4 k3 0 (tl) 10 i/o pl10c dout l21t_a0 l31t_d1 a26 ??? v dd 15 v dd 15 ??? j3 j1 0 (tl) 10 i/o pl11d vref_0_10 l22c_a0 l32c_a0 j2 k2 0 (tl) 10 i/o pl11c a16/ppc_a30 l22t_a0 l32t_a0 ? b33 ?? vss vss ??? ? k1 0 (tl) 10 i/o pl11a ??? j1 m5 7 (cl) 1 i/o pl12d a15/ppc_a29 l1c_d0 l1c_a0 k2 l4 7 (cl) 1 i/o pl12c a14/ppc_a28 l1t_d0 l1t_a0
agere systems inc. 49 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s k1 l1 7 (cl) ? v dd io7 v dd io7 ??? ? m4 7 (cl) 1 i/o pl12b ?? l2c_a0 ? n5 7 (cl) 1 i/o pl12a ?? l2t_a0 k3 l3 7 (cl) 1 i/o pl13d vref_7_01 l2c_a0 l3c_a0 l3 l2 7 (cl) 1 i/o pl13c d4 l2t_a0 l3t_a0 u16 b34 ?? vss vss ??? ? n4 7 (cl) 2 i/o pl13b ?? l4c_a0 ? p5 7 (cl) 2 i/o pl13a ?? l4t_a0 l4 m2 7 (cl) 2 i/o pl14d rdy/busy_n/rclk l3c_a0 l5c_a0 m4 m1 7 (cl) 2 i/o pl14c vref_7_02 l3t_a0 l5t_a0 l2 m3 7 (cl) ? v dd io7 v dd io7 ??? l1 n3 7 (cl) 2 i/o pl15d a13/ppc_a27 l4c_a0 l6c_a0 m1 n2 7 (cl) 2 i/o pl15c a12/ppc_a26 l4t_a0 l6t_a0 u17 c3 ?? vss vss ??? m3 p4 7 (cl) 3 i/o pl16d ? l5c_a0 l7c_a0 m2 p3 7 (cl) 3 i/o pl16c ? l5t_a0 l7t_a0 ? r3 7 (cl) ? v dd io7 v dd io7 ??? ? r5 7 (cl) 3 i/o pl16a ??? n1 n1 7 (cl) 3 i/o pl17d a11/ppc_a25 l6c_a0 l8c_a0 n2 p2 7 (cl) 3 i/o pl17c vref_7_03 l6t_a0 l8t_a0 ae1 c13 ?? vss vss ??? ? r4 7 (cl) 3 i/o pl17a ??? ? p1 7 (cl) 3 i/o pl18d ?? l9c_a0 ? r2 7 (cl) 3 i/o pl18c ?? l9t_a0 u14 ??? v dd 15 v dd 15 ??? ? t2 7 (cl) 3 i/o pl18b ?? l10c_a0 ? r1 7 (cl) 3 i/o pl18a ?? l10t_a0 n3 t5 7 (cl) 4 i/o pl19d rd_n/mpi_strb_n l7c_a0 l11c_a0 n4 t4 7 (cl) 4 i/o pl19c vref_7_04 l7t_a0 l11t_a0 ae26 c22 ?? vss vss ??? ? u5 7 (cl) 4 i/o pl19b ?? l12c_d1 ? t3 7 (cl) 4 i/o pl19a ?? l12t_d1 p4 t1 7 (cl) 4 i/o pl20d plck0c l8c_a0 l13c_d1 p3 u3 7 (cl) 4 i/o pl20c plck0t l8t_a0 l13t_d1 p2 u1 7 (cl) ? v dd io7 v dd io7 ??? ? u4 7 (cl) 4 i/o pl20b ?? l14c_a1 ? u2 7 (cl) 4 i/o pl20a ?? l14t_a1 af1 ??? v dd 15 v dd 15 ??? af2 c32 ?? vss vss ??? p1 v1 7 (cl) 5 i/o pl21d a10/ppc_a24 l9c_a0 l15c_a0 r1 v2 7 (cl) 5 i/o pl21c a9/ppc_a23 l9t_a0 l15t_a0 af25 d4 ?? vss vss ??? ? v3 7 (cl) 5 i/o pl21b ?? l16c_a0 ? v4 7 (cl) 5 i/o pl21a ?? l16t_a0 r2 v5 7 (cl) 5 i/o pl22d a8/ppc_a22 l10c_a0 l17c_a0 pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
50 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s r3 w4 7 (cl) 5 i/o pl22c vref_7_05 l10t_a0 l17t_a0 af26 ??? v dd 15 v dd 15 ??? ? w3 7 (cl) 5 i/o pl23d ?? l18c_a0 ? w2 7 (cl) 5 i/o pl23c ?? l18t_a0 ? d30 ?? vss vss ??? ? y1 7 (cl) 5 i/o pl23a ??? t1 w5 7 (cl) 6 i/o pl24d plck1c l11c_a0 l19c_a0 t2 y4 7 (cl) 6 i/o pl24c plck1t l11t_a0 l19t_a0 ? w1 7 (cl) ? v dd io7 v dd io7 ??? ? y2 7 (cl) 6 i/o pl24a ??? t4 y5 7 (cl) 6 i/o pl25d vref_7_06 l12c_a0 l20c_d1 r4 aa3 7 (cl) 6 i/o pl25c a7/ppc_a21 l12t_a0 l20t_d1 ? d31 ?? vss vss ??? ? aa2 7 (cl) 6 i/o pl25a ??? u1 aa1 7 (cl) 6 i/o pl26d a6/ppc_a20 l13c_a0 l21c_a0 u2 ab1 7 (cl) 6 i/o pl26c a5/ppc_a19 l13t_a0 l21t_a0 t3 y3 7 (cl) ? v dd io7 v dd io7 ??? v1 aa4 7 (cl) 7 i/o pl26b ??? v2 ab2 7 (cl) 7 i/o pl27d wr_n/mpi_rw l14c_d0 l22c_a0 u3 ab3 7 (cl) 7 i/o pl27c vref_7_07 l14t_d0 l22t_a0 ? aa5 7 (cl) 7 i/o pl27b ?? l23c_a0 ? ab4 7 (cl) 7 i/o pl27a ?? l23t_a0 w1 ac2 7 (cl) 8 i/o pl28d a4/ppc_a18 l15c_a0 l23c_a0 y1 ac1 7 (cl) 8 i/o pl28c vref_7_08 l15t_a0 l23t_a0 ? ac3 7 (cl) ? v dd io7 v dd io7 ??? v4 ab5 7 (cl) 8 i/o pl29d a3/ppc_a17 l16c_a0 l23c_a0 u4 ac4 7 (cl) 8 i/o pl29c a2/ppc_a16 l16t_a0 l23t_a0 ? d33 ?? vss vss ??? ? ad2 7 (cl) 8 i/o pl29a ??? v3 ac5 7 (cl) 8 i/o pl30d a1/ppc_a15 l17c_d0 l24c_d1 w2 ad3 7 (cl) 8 i/o pl30c a0/ppc_a14 l17t_d0 l24t_d1 y2 ae1 7 (cl) 8 i/o pl31d dp0 l18c_d0 l25c_a0 w3 ae2 7 (cl) 8 i/o pl31c dp1 l18t_d0 l25t_a0 ? e34 ?? vss vss ??? ? af1 7 (cl) 8 i/o pl31a ??? aa1 ad5 6 (bl) 1 i/o pl32d d8 l1c_a0 l1c_a0 aa2 ad4 6 (bl) 1 i/o pl32c vref_6_01 l1t_a0 l1t_a0 ? ak4 6 (bl) ? v dd io6 v dd io6 ??? ? ae3 6 (bl) 1 i/o pl32a ??? y3 ae5 6 (bl) 1 i/o pl33d d9 l2c_d0 l2c_a0 w4 ae4 6 (bl) 1 i/o pl33c d10 l2t_d0 l2t_a0 t16 f33 ?? vss vss ??? y4 af2 6 (bl) 2 i/o pl34d ? l3c_d0 l3c_a0 aa3 ag1 6 (bl) 2 i/o pl34c vref_6_02 l3t_d0 l3t_a0 ab1 ak5 6 (bl) ? v dd io6 v dd io6 ??? pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 51 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ? af3 6 (bl) 2 i/o pl34b ?? l4c_a1 ? af5 6 (bl) 2 i/o pl34a ?? l4t_a1 t17 h34 ?? vss vss ??? ab2 ag2 6 (bl) 3 i/o pl35b d11 l4c_d0 l5c_d1 ac1 af4 6 (bl) 3 i/o pl35a d12 l4t_d0 l5t_d1 ? ah1 6 (bl) 3 i/o pl36d ?? l6c_d1 ? ag3 6 (bl) 3 i/o pl36c ?? l6t_d1 ? al1 6 (bl) ? v dd io6 v dd io6 ??? ac2 ah2 6 (bl) 3 i/o pl36b vref_6_03 l5c_d0 l7c_a0 ab3 aj1 6 (bl) 3 i/o pl36a d13 l5t_d0 l7t_a0 ? ag4 6 (bl) 4 i/o pl37d ??? u10 j33 ?? vss vss ??? ? ah3 6 (bl) 4 i/o pl37b ?? l8c_d1 ad1 ag5 6 (bl) 4 i/o pl37a vref_6_04 ? l8t_d1 ? aj2 6 (bl) 4 i/o pl38c ??? ? al3 6 (bl) ? v dd io6 v dd io6 ??? ? ak1 6 (bl) 4 i/o pl38b ??? ? ah4 6 (bl) 4 i/o pl38a ??? aa4 aj3 6 (bl) 4 i/o pl39d pll_ck7c/hppll l6c_a0 l9c_a0 ab4 ak2 6 (bl) 4 i/o pl39c pll_ck7t/hppll l6t_a0 l9t_a0 u11 l34 ?? vss vss ??? ? ah5 6 (bl) 4 i/o pl39b ?? l10c_a0 ? aj4 6 (bl) 4 i/o pl39a ?? l10t_a0 u12 n13 ?? vss vss ??? ac3 ak3 ?? iptemp ptemp ?? ad2 am1 6 (bl) ? v dd io6 v dd io6 ??? r14 ??? v dd 15 v dd 15 ??? ae2 an1 ?? i/o lvds_r lvds_r ?? ad3 aj5 ?? v dd 33 v dd 33 ??? u15 n14 ?? vss vss ??? ac4 al5 ?? v dd 33 v dd 33 ??? t13 ??? v dd 15 v dd 15 ??? ae3 am5 6 (bl) 5 i/o pb2a dp2 ? l11t_a0 ? an4 6 (bl) 5 i/o pb2b ?? l11c_a0 ? am2 6 (bl) ? v dd io6 v dd io6 ??? ac5 ak6 6 (bl) 5 i/o pb2c pll_ck6t/ppll l7t_d0 l12t_a0 ad4 al6 6 (bl) 5 i/o pb2d pll_ck6c/ppll l7c_d0 l12c_a0 ? ak7 6 (bl) 5 i/o pb3a ??? ? n15 ?? vss vss ??? ? an5 6 (bl) 5 i/o pb3c ?? l13t_a0 ? am6 6 (bl) 5 i/o pb3d ?? l13c_a0 ae4 an6 6 (bl) 5 i/o pb4a vref_6_05 l8t_d0 l14t_a0 af3 ap5 6 (bl) 5 i/o pb4b dp3 l8c_d0 l14c_a0 ? am4 6 (bl) ? v dd io6 v dd io6 ??? ac6 al7 6 (bl) 6 i/o pb4c ? l9t_d0 l15t_a0 pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
52 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ad5 am7 6 (bl) 6 i/o pb4d ? l9c_d0 l15c_a0 ? n20 ?? vss vss ??? af4 an7 6 (bl) 6 i/o pb5c vref_6_06 l10t_d0 l16t_a0 ae5 ap6 6 (bl) 6 i/o pb5d d14 l10c_d0 l16c_a0 ? ak8 6 (bl) 6 i/o pb6a ?? l17t_a0 ad6 al8 6 (bl) 6 i/o pb6b ?? l17c_a0 af5 an3 6 (bl) ? v dd io6 v dd io6 ??? ac7 am8 6 (bl) 7 i/o pb6c d15 l11t_a0 l18t_d1 ac8 ak9 6 (bl) 7 i/o pb6d d16 l11c_a0 l18c_d1 ? ap7 6 (bl) 7 i/o pb7a ??? ? n21 ?? vss vss ??? ad7 al9 6 (bl) 7 i/o pb7c d17 l12t_d0 l19t_a0 ae6 ak10 6 (bl) 7 i/o pb7d d18 l12c_d0 l19c_a0 ? an8 6 (bl) 7 i/o pb8a ??? ? ap2 6 (bl) ? v dd io6 v dd io6 ??? ae7 am9 6 (bl) 7 i/o pb8c vref_6_07 l13t_d0 l20t_a0 ad8 al10 6 (bl) 7 i/o pb8d d19 l13c_d0 l20c_a0 ? ap8 6 (bl) 8 i/o pb9a ??? ? n22 ?? vss vss ??? af6 al11 6 (bl) 8 i/o pb9c d20 l14t_a0 l21t_a0 af7 ak11 6 (bl) 8 i/o pb9d d21 l14c_a0 l21c_a0 ? am10 6 (bl) 8 i/o pb10a ??? t14 ??? v dd 15 v dd 15 ??? ae8 an9 6 (bl) 8 i/o pb10c vref_6_08 l15t_d0 l22t_a0 ad9 ap9 6 (bl) 8 i/o pb10d d22 l15c_d0 l22c_a0 ? am11 6 (bl) 9 i/o pb11a ?? l23t_d1 ? ak12 6 (bl) 9 i/o pb11b ?? l23c_d1 ? p13 ?? vss vss ??? ac9 an10 6 (bl) 9 i/o pb11c d23 l16t_a0 l24t_a0 ac10 ap10 6 (bl) 9 i/o pb11d d24 l16c_a0 l24c_a0 ? al12 6 (bl) 9 i/o pb12a ?? l25t_a0 ? ak13 6 (bl) 9 i/o pb12b ?? l25c_a0 ? ap3 6 (bl) ? v dd io6 v dd io6 ??? af8 an11 6 (bl) 9 i/o pb12c vref_6_09 l17t_d0 l26t_a0 ae9 an12 6 (bl) 9 i/o pb12d d25 l17c_d0 l26c_a0 ? ak14 6 (bl) 9 i/o pb13a ?? l27t_a0 ? al13 6 (bl) 9 i/o pb13b ?? l27c_a0 ? p14 ?? vss vss ??? ad10 ap12 6 (bl) 10 i/o pb13c d26 l18t_a0 l28t_a0 ae10 an13 6 (bl) 10 i/o pb13d d27 l18c_a0 l28c_a0 ? al14 6 (bl) 10 i/o pb14a ?? l29t_a0 ? ak15 6 (bl) 10 i/o pb14b ?? l29c_a0 af9 ? 6 (bl) ? v dd io6 v dd io6 ??? ae11 ap13 6 (bl) 10 i/o pb14c vref_6_10 l19t_a0 l30t_a0 ad11 ap14 6 (bl) 10 i/o pb14d d28 l19c_a0 l30c_a0 pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 53 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ? an14 6 (bl) 11 i/o pb15a ??? ? p15 ?? vss vss ??? ac12 am14 6 (bl) 11 i/o pb15c d29 l20t_a0 l31t_a0 ac11 al15 6 (bl) 11 i/o pb15d d30 l20c_a0 l31c_a0 ? an15 6 (bl) 11 i/o pb16a ??? af10 am16 6 (bl) 11 i/o pb16c vref_6_11 l21t_a0 l32t_a0 af11 al16 6 (bl) 11 i/o pb16d d31 l21c_a0 l32c_a0 ? ap15 5 (bc) 1 i/o pb17a ??? r16 p20 ?? vss vss ??? ad12 an16 5 (bc) 1 i/o pb17c ? l1t_a0 l1t_a0 ae12 ap16 5 (bc) 1 i/o pb17d ? l1c_a0 l1c_a0 ? ak16 5 (bc) 1 i/o pb18a ??? p16 ??? v dd 15 v dd 15 ??? af12 al17 5 (bc) 1 i/o pb18c vref_5_01 l2t_a0 l2t_a0 af13 ak17 5 (bc) 1 i/o pb18d ? l2c_a0 l2c_a0 p17 ??? v dd 15 v dd 15 ??? r17 p21 ?? vss vss ??? ? am17 5 (bc) 2 i/o pb19a ?? l3t_a0 ? an17 5 (bc) 2 i/o pb19b ?? l3c_a0 t10 p22 ?? vss vss ??? ad13 ap18 5 (bc) 2 i/o pb19c pbck0t l3t_a0 l4t_a1 ae13 am18 5 (bc) 2 i/o pb19d pbck0c l3c_a0 l4c_a1 ? an18 5 (bc) 2 i/o pb20a ?? l5t_a1 ? al18 5 (bc) 2 i/o pb20b ?? l5c_a1 af14 am12 5 (bc) ? v dd io5 v dd io5 ??? ac14 an19 5 (bc) 2 i/o pb20c vref_5_02 l4t_a0 l6t_d2 ac13 ak18 5 (bc) 2 i/o pb20d ? l4c_a0 l6c_2 ? am19 5 (bc) 2 i/o pb21a ?? l7t_d1 ? ap20 5 (bc) 2 i/o pb21b ?? l7c_d1 r13 ??? v dd 15 v dd 15 ??? ae14 al19 5 (bc) 3 i/o pb21c ? l5t_a0 l8t_d1 ad14 an20 5 (bc) 3 i/o pb21d vref_5_03 l5c_a0 l8c_d1 ? ap21 5 (bc) 3 i/o pb22a ??? t11 p34 ?? vss vss ??? af15 al20 5 (bc) 3 i/o pb22c ? l6t_a0 l9t_a0 ae15 ak19 5 (bc) 3 i/o pb22d ? l6c_a0 l9c_a0 ? an21 5 (bc) 3 i/o pb23a ??? af16 am15 5 (bc) ? v dd io5 v dd io5 ??? ad15 ak20 5 (bc) 3 i/o pb23c pbck1t l7t_d0 l10t_d1 ae16 am21 5 (bc) 3 i/o pb23d pbck1c l7c_d0 l10c_d1 ? ap22 5 (bc) 3 i/o pb24a ??? t12 r13 ?? vss vss ??? ac15 al21 5 (bc) 4 i/o pb24c ? l8t_a0 l11t_d1 ac16 an22 5 (bc) 4 i/o pb24d ? l8c_a0 l11c_d1 ? ap23 5 (bc) 4 i/o pb25a ??? pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
54 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s af17 am20 5 (bc) ? v dd io5 v dd io5 ??? ad16 an23 5 (bc) 4 i/o pb25c ? l9t_d0 l12t_a0 ae17 an24 5 (bc) 4 i/o pb25d vref_5_04 l9c_d0 l12c_a0 ? ak21 5 (bc) 4 i/o pb26a ?? l13t_a0 ? al22 5 (bc) 4 i/o pb26b ?? l13c_a0 t15 r14 ?? vss vss ??? af18 ap25 5 (bc) 5 i/o pb26c ? l10t_a0 l14t_d1 ae18 am24 5 (bc) 5 i/o pb26d vref_5_05 l10c_a0 l14c_d1 ? ak22 5 (bc) 5 i/o pb27a ?? l15t_a0 ? al23 5 (bc) 5 i/o pb27b ?? l15c_a0 ad17 am23 5 (bc) ? v dd io5 v dd io5 ??? af19 an25 5 (bc) 5 i/o pb27c ? l11t_a0 l16t_d1 af20 al24 5 (bc) 5 i/o pb27d ? l11c_a0 l16t_d1 ? ap26 5 (bc) 6 i/o pb28a ??? ? r15 ?? vss vss ??? ac18 am25 5 (bc) 6 i/o pb28c ? l12t_a0 l17t_d1 ac17 ak23 5 (bc) 6 i/o pb28d vref_5_06 l12c_a0 l17c_d1 ? an26 5 (bc) 6 i/o pb29a ??? ? al25 5 (bc) 6 i/o pb29c ?? l18t_a0 ? ak24 5 (bc) 6 i/o pb29d ?? l18c_a0 ? ap27 5 (bc) 7 i/o pb30a ??? ? r20 ?? vss vss ??? ad18 am26 5 (bc) 7 i/o pb30c ? l13t_d0 l19t_a0 ae19 an27 5 (bc) 7 i/o pb30d ? l13c_d0 l19c_a0 ? ap11 5 (bc) ? v dd io5 v dd io5 ??? ae20 ap28 5 (bc) 7 i/o pb31c vref_5_07 l14t_d0 l20t_d1 ad19 am27 5 (bc) 7 i/o pb31d ? l14c_d0 l20c_d1 ? r21 ?? vss vss ??? af21 al26 5 (bc) 7 i/o pb32c ? l15t_a0 l21t_a0 ae21 ak25 5 (bc) 7 i/o pb32d ? l15c_a0 l21c_a0 ad20 ap17 5 (bc) ? v dd io5 v dd io5 ??? ac19 an28 5 (bc) 8 i/o pb33c ?? l22t_a0 ? ap29 5 (bc) 8 i/o pb33d vref_5_08 ? l22c_a0 ? r22 ?? vss vss ??? ? ap19 5 (bc) ? v dd io5 v dd io5 ??? ? t16 ?? vss vss ??? ? t17 ?? vss vss ??? m14 a31 ?? v dd 15 v dd 15 ??? ac20 al27 ?? i rx_dat_in_10_p/ rx_dat_in_0_p ? l1_d2 l1_a0 af22 am28 ?? i rx_dat_in_10_n/ rx_dat_in_0_n ? l1_d2 l1_a0 n10 c30 ?? v dd 15 vdd15 ??? ae22 an29 ?? i rx_dat_in_11_p/ rx_dat_in_1_p ? l2_d0 l2_a0 note: the pin description for rx_dat_in* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 55 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ad21 ap30 ?? i rx_dat_in_11_n/ rx_dat_in_1_n ? l2_d0 l2_a0 af23 ??? v dd 33 v dd 33 ? ?? ae23 al28 ?? i rx_dat_in_12_p/ rx_dat_in_2_p ? l3_d0 l3_a0 af24 am29 ?? i rx_dat_in_12_n/ rx_dat_in_2_n ? l3_d0 l3_a0 l12 y34 ?? vss vss ??? ? an30 ?? v dd 33 v dd 33 ??? ac21 ak27 ?? i rx_dat_in_13_p/ rx_dat_in_3_p ? l4_d0 l4_a0 ad22 ak28 ?? i rx_dat_in_13_n/ rx_dat_in_3_n ? l4_d0 l4_a0 ad23 al29 ?? i rx_clk_in_0_p ? l5_d0 l5_a0 ae24 am30 ?? i rx_clk_in_0_n ? l5_d0 l5_a0 ac22 an31 ?? i lvctap_1 ??? ac23 ap32 ?? vssa_4 vssa_4 ??? ad24 ak30 ?? v dd 33a_4 v dd 33a_4 ??? l15 aa13 ?? vss vss ??? l16 aa14 ?? vss vss ??? n11 c33 ?? v dd 15 v dd 15 ??? ae25 ak31 ?? v dd 33a_5 v dd 33a_5 ??? ac24 aj30 ?? v dd 33 v dd 33 ??? ad25 ak32 ?? vssa_5 vssa_5 ??? ad26 aj31 ?? i lvctap_2 ??? l17 aa15 ?? vss vss ??? ? ah30 ?? v dd 33 v dd 33 ??? n12 c34 ?? v dd 15 v dd 15 ??? ab23 ak33 ?? i rx_dat_in_20_p/ rx_dat_in_4_p ? l6_a0 l6_a0 aa23 aj32 ?? i rx_dat_in_20_n/ rx_dat_in_4_n ? l6_a0 l6_a0 ac25 ah31 ?? i rx_dat_in_21_p/ rx_dat_in_5_p ? l7_d0 l7_a0 ab24 ag30 ?? i rx_dat_in_21_n/ rx_dat_in_5_n ? l7_d0 l7_a0 m10 aa20 ?? vss vss ??? ab25 af30 ?? i rx_dat_in_22_p/ rx_dat_in_6_p ? l8_d0 l8_a0 aa24 ag31 ?? i rx_dat_in_22_n/ rx_dat_in_6_n ? l8_d0 l8_a0 ac26 ak34 ?? i rx_dat_in_23_p/ rx_dat_in_7_p ? l9_a0 l9_a0 ab26 aj33 ?? i rx_dat_in_23_n/ rx_dat_in_7_n ? l9_a0 l9_a0 n15 d28 ?? v dd 15 v dd 15 ??? note: the pin description for rx_dat_in* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
56 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s m11 aa21 ?? vss vss ??? y24 ah32 ?? v dd 33 v dd 33 ??? w23 ae30 ?? i lvctap_3 ??? m12 aa22 ?? vss vss ??? n16 d32 ?? v dd 15 v dd 15 ??? aa25 ag32 ?? i rx_clk_in_1_p ? l10_a0 l10_a0 aa26 af31 ?? i rx_clk_in_1_n ? l10_a0 l10_a0 ? af32 ?? v dd 33 v dd 33 ??? m15 ab13 ?? vss vss ??? y23 ac30 ?? i rx_dat_in_30_p/ rx_dat_in_8_p ? l11_d0 l11_a0 w24 ad30 ?? i rx_dat_in_30_n/ rx_dat_in_8_n ? l11_d0 l11_a0 n17 d34 ?? v dd 15 v dd 15 ??? y25 ae31 ?? i rx_dat_in_31_p/ rx_dat_in_9_p ? l12_a0 l12_a0 y26 ae32 ?? i rx_dat_in_31_n/ rx_dat_in_9_n ? l12_a0 l12_a0 m16 ab14 ?? vss vss ??? ? af33 ?? v dd 33 v dd 33 ??? w25 ad31 ?? i rx_dat_in_32_p/ rx_dat_in_10_p ? l13_d0 l13_a0 v24 ad32 ?? i rx_dat_in_32_n/ rx_dat_in_10_n ? l13_d0 l13_a0 p10 f34 ?? v dd 15 v dd 15 ??? w26 ab30 ?? i lvctap_4 ??? v23 ac31 ?? i rx_dat_in_33_p/ rx_dat_in_11_p ? l14_a0 l14_a0 u23 ac32 ?? i rx_dat_in_33_n/ rx_dat_in_11_n ? l14_a0 l14_a0 ? ac33 ?? v dd 33 v dd 33 ??? m17 ab15 ?? vss vss ??? v25 ab31 ?? i rx_clk_in_2_p ? l15_d0 l15_a0 u24 ab32 ?? i rx_clk_in_2_n ? l15_d0 l15_a0 v26 aa30 ?? i lvctap_5 ??? p11 g33 ?? v dd 15 v dd 15 ??? u26 ab33 ?? v dd 33 v dd 33 ??? n13 ab20 ?? vss vss ??? u25 aa31 ?? i rx_clk_in_3_p ? l16_d0 l16_a0 t24 y30 ?? i rx_clk_in_3_n ? l16_d0 l16_a0 r23 aa32 ?? i rx_dat_in_40_p/ rx_dat_in_12_p ? l17_a0 l17_a0 t23 aa33 ?? i rx_dat_in_40_n/ rx_dat_in_12_n ? l17_a0 l17_a0 n14 ab21 ?? vss vss ??? note: the pin description for rx_dat_in* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 57 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s p12 g34 ?? v dd 15 v dd 15 ??? t25 y31 ?? i rx_dat_in_41_p/ rx_dat_in_13_p ? l18_a0 l18_a0 t26 y32 ?? i rx_dat_in_41_n/ rx_dat_in_13_n ? l18_a0 l18_a0 ? w30 ?? v dd 33 v dd 33 ??? p13 ab22 ?? vss vss ??? ? y33 ?? v dd 33 v dd 33 ??? ? j34 ?? v dd 15 v dd 15 ??? r24 w31 ?? i rx_dat_in_42_p/ rx_dat_in_14_p ? l19_a0 l19_a0 r25 w32 ?? i rx_dat_in_42_n/ rx_dat_in_14_n ? l19_a0 l19_a0 p14 ac34 ?? vss vss ??? p15 k33 ?? v dd 15 v dd 15 ??? r26 v30 ?? i rx_dat_in_43_p/ rx_dat_in_15_p ? l20_d0 l20_a0 p25 v31 ?? i rx_dat_in_43_n/ rx_dat_in_15_n ? l20_d0 l20_a0 p24 w33 ?? v dd 33 v dd 33 ??? r10 ae33 ?? vss vss ??? p26 v32 ?? ilv_ref10 ??? n26 v33 ?? ilv_ref14 ??? n23 u33 ?? i lv_reshi ??? p23 u31 ?? i lv_reslo ??? r11 af34 ?? vss vss ??? ? u30 ?? v dd 33 v dd 33 ??? ? k34 ?? v dd 15 v dd 15 ??? n25 u32 ?? o tx_clk_out_0_p ? l21_a0 l21_a0 n24 t33 ?? o tx_clk_out_0_n ? l21_a0 l21_a0 r12 ah33 ?? vss vss ??? ? t32 ?? v dd 33 v dd 33 ??? m26 t31 ?? o tx_dat_out_10_p/ tx_dat_out_0_p ? l22_a0 l22_a0 m25 t30 ?? o tx_dat_out_10_n/ tx_dat_out_0_n ? l22_a0 l22_a0 r15 aj34 ?? vss vss ??? m24 r33 ?? o tx_dat_out_11_p/ tx_dat_out_1_p ? l23_a0 l23_a0 m23 r32 ?? o tx_dat_out_11_n/ tx_dat_out_1_n ? l23_a0 l23_a0 ? m34 ?? v dd 15 v dd 15 ??? l26 r31 ?? o tx_dat_out_12_p/ tx_dat_out_2_p ? l24_a0 l24_a0 l25 r30 ?? o tx_dat_out_12_n/ tx_dat_out_2_n ? l24_a0 l24_a0 note: the pin descriptions for rx_dat_in* and tx_dat_out* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
58 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ? al2 ?? vss vss ??? k26 ??? v dd 33 v dd 33 ??? ? p33 ?? v dd 33 v dd 33 ??? l24 n33 ?? o tx_dat_out_13_p/ tx_dat_out_3_p ? l25_a0 l25_a0 l23 p32 ?? o tx_dat_out_13_n/ tx_dat_out_3_n ? l25_a0 l25_a0 j26 p30 ?? o tx_clk_out_1_p ? l26_d0 l26_a0 k25 p31 ?? o tx_clk_out_1_n ? l26_d0 l26_a0 ? al4 ?? vss vss ??? j25 n32 ?? o tx_dat_out_20_p/ tx_dat_out_4_p ? l27_d0 l27_a0 k24 n31 ?? o tx_dat_out_20_n/ tx_dat_out_4_n ? l27_d0 l27_a0 ? n16 ?? v dd 15 v dd 15 ??? ? n30 ?? v dd 33 v dd 33 ??? h26 m33 ?? o tx_dat_out_21_p/ tx_dat_out_5_p ? l28_a0 l28_a0 g26 m32 ?? o tx_dat_out_21_n/ tx_dat_out_5_n ? l28_a0 l28_a0 ? al30 ?? vss vss ??? k23 m31 ?? o tx_dat_out_22_p/ tx_dat_out_6_p ? l29_a0 l29_a0 j23 m30 ?? o tx_dat_out_22_n/ tx_dat_out_6_n ? l29_a0 l29_a0 ? l33 ?? v dd 33 v dd 33 ??? ? n17 ?? v dd 15 v dd 15 ??? j24 l32 ?? o tx_dat_out_23_p/ tx_dat_out_7_p ? l30_d0 l30_a0 h25 k32 ?? o tx_dat_out_23_n/ tx_dat_out_7_n ? l30_d0 l30_a0 ? al31 ?? vss vss ??? h24 l30 ?? o tx_clk_out_2_p ? l31_d0 l31_a0 g25 l31 ?? o tx_clk_out_2_n ? l31_d0 l31_a0 ? n18 ?? v dd 15 v dd 15 ??? e26 j31 ?? o tx_dat_out_30_p/ tx_dat_out_8_p ? l32_a0 l32_a0 f26 k31 ?? o tx_dat_out_30_n/ tx_dat_out_8_n ? l32_a0 l32_a0 ? k30 ?? v dd 33 v dd 33 ??? ? am3 ?? vss vss ??? g24 h33 ?? o tx_dat_out_31_p/ tx_dat_out_9_p ? l33_d0 l33_a0 h23 j32 ?? o tx_dat_out_31_n/ tx_dat_out_9_n ? l33_d0 l33_a0 g23 h32 ?? v dd 33 v dd 33 ??? note: the pin description for tx_dat_out* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 59 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s f25 h31 ?? i tx_clk_in_p ? l34_a0 l34_a0 e25 j30 ?? i tx_clk_in_n ? l34_a0 l34_a0 ? n19 ?? v dd 15 v dd 15 ??? f24 g32 ?? i lvctap_6 ??? ? am13 ?? vss vss ??? d26 g31 ?? o tx_dat_out_32_p/ tx_dat_out_10_p ? l35_a0 l35_a0 d25 f32 ?? o tx_dat_out_32_n/ tx_dat_out_10_n ? l35_a0 l35_a0 ? n34 ?? v dd 15 v dd 15 ??? ? h30 ?? v dd 33 v dd 33 ??? c25 e33 ?? o tx_dat_out_33_p/ tx_dat_out_11_p ? l36_d0 l36_a0 d24 e32 ?? o tx_dat_out_33_n/ tx_dat_out_11_n ? l36_d0 l36_a0 ? am22 ?? vss vss ??? f23 f31 ?? o tx_clk_out_3_p ? l37_d0 l37_a0 e24 e31 ?? o tx_clk_out_3_n ? l37_d0 l37_a0 ? g30 ?? v dd 33 v dd 33 ??? ? p16 ?? v dd 15 v dd 15 ??? c26 f30 ?? v dd 33 v dd 33 ??? b25 e30 ?? vssa_6 vssa_6 ??? e23 b32 ?? v dd 33 v dd 33 ??? c24 c31 ?? v dd 33a_6 v dd 33a_6 ??? ? am32 ?? vss vss ??? ? an2 ?? vss vss ??? d23 e29 ?? v dd 33a_7 v dd 33a_7 ??? b24 e28 ?? vssa_7 vssa_7 ??? d22 a32 ?? o tx_dat_out_40_n/ tx_dat_out_12_n ? l38_d0 l38_a0 c23 b31 ?? o tx_dat_out_40_p/ tx_dat_out_12_p ? l38_d0 l38_a0 a24 e27 ?? o tx_dat_out_41_n/ tx_dat_out_13_n ? l39_d0 l39_a0 b23 e26 ?? o tx_dat_out_41_p/ tx_dat_out_13_p ? l39_d0 l39_a0 c22 b30 ?? v dd 33 v dd 33 ??? ? p17 ?? v dd 15 v dd 15 ??? d21 d29 ?? o tx_dat_out_42_n/ tx_dat_out_14_n ? l40_a0 l40_a0 c21 c29 ?? o tx_dat_out_42_p/ tx_dat_out_14_p ? l40_a0 l40_a0 ? an33 ?? vss vss ??? a23 c28 ?? o tx_dat_out_43_n/ tx_dat_out_15_n ? l41_d0 l41_a0 note: the pin description for tx_dat_out* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
60 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s b22 d27 ?? o tx_dat_out_43_p/ tx_dat_out_15_p ? l41_d0 l41_a0 a22 a30 ?? i pwrdn ??? b21 e25 ?? i reset_rx ??? d20 b29 ?? i reset_tx ??? d19 a29 ?? i pll_bypass ??? k12 t18 ?? vss vss ??? k15 t19 ?? vss vss ??? ? a11 1 (tc) ? v dd io1 v dd io1 ??? k16 u16 ?? vss vss ??? ? a17 1 (tc) ? v dd io1 v dd io1 ??? ? c27 1 (tc) 9 i/o pt32d ??? c20 d26 1 (tc) 9 i/o pt32c ??? k17 u17 ?? vss vss ??? b20 b28 1 (tc) 10 i/o pt31d ? l1c_d0 l1c_a0 c19 a28 1 (tc) 10 i/o pt31c vref_1_10 l1t_d0 l1t_a0 ? a19 1 (tc) ? v dd io1 vddio1 ??? ? b27 1 (tc) 10 i/o pt30d ??? l10 u18 ?? vss vss ??? ? c26 1 (tc) 10 i/o pt30a ??? a21 b26 1 (tc) 10 i/o pt29d ? l2c_a0 l2c_a0 a20 a27 1 (tc) 10 i/o pt29c ? l2t_a0 l2t_a0 l13 ??? v dd 15 v dd 15 ??? ? e24 1 (tc) 10 i/o pt29b ?? l3c_a0 ? d25 1 (tc) 10 i/o pt29a ?? l3t_a0 b19 d24 1 (tc) 1 i/o pt28d ? l3c_d0 l4c_a0 c18 c25 1 (tc) 1 i/o pt28c ? l3t_d0 l4t_a0 l11 u19 ?? vss vss ??? ? b25 1 (tc) 1 i/o pt28b ?? l5c_a0 ? a26 1 (tc) 1 i/o pt28a ?? l5t_a0 d18 e23 1 (tc) 1 i/o pt27d vref_1_01 l4c_a0 l6c_a0 d17 d23 1 (tc) 1 i/o pt27c ? l4t_a0 l6t_a0 a19 a24 1 (tc) ? v dd io1 v dd io1 ??? b18 c24 1 (tc) 1 i/o pt27b ? l5c_d0 l7c_d1 c17 a25 1 (tc) 1 i/o pt27a ? l5t_d0 l7t_d1 a18 e22 1 (tc) 2 i/o pt26d ? l6c_d0 l8c_a0 b17 e21 1 (tc) 2 i/o pt26c vref_1_02 l6t_d0 l8t_a0 ? u34 ?? vss vss ??? ? b24 1 (tc) 2 i/o pt26b ?? l9c_d1 ? d22 1 (tc) 2 i/o pt26a ?? l9t_d1 a17 b23 1 (tc) 2 i/o pt25d ? l7c_d0 l10c_a0 b16 a23 1 (tc) 2 i/o pt25c ? l7t_d0 l10t_a0 d15 c12 1 (tc) ? v dd io1 v dd io1 ??? d16 d21 1 (tc) 3 i/o pt24d ? l8c_a0 l11c_d1 note: the pin description for tx_dat_out* shows both the naming conventions, 2.5 gbit/10 gbit, where only one is valid depending on the mode of operation. pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 61 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s c16 b22 1 (tc) 3 i/o pt24c vref_1_03 l8t_a0 l11t_d1 ? v16 ?? vss vss ??? ? a22 1 (tc) 3 i/o pt24a ??? a16 d20 1 (tc) 3 i/o pt23d ? l9c_a0 l12c_a0 a15 e20 1 (tc) 3 i/o pt23c ? l9t_a0 l12t_a0 b15 c15 1 (tc) ? v dd io1 v dd io1 ??? ? c21 1 (tc) 3 i/o pt23a ??? ? b21 1 (tc) 3 i/o pt22d ?? l13c_a0 ? a21 1 (tc) 3 i/o pt22c ?? l13t_a0 ? v17 ?? vss vss ??? ? b20 1 (tc) 3 i/o pt22a ??? c15 c19 1 (tc) 4 i/o pt21d ? l10c_a0 l14c_d1 c14 a20 1 (tc) 4 i/o pt21c ? l10t_a0 l14t_d1 l14 ??? v dd 15 v dd 15 ??? ? d19 1 (tc) 4 i/o pt20d ?? l15c_a0 ? e19 1 (tc) 4 i/o pt20c ?? l15t_a0 ? v18 ?? vss vss ??? b14 b19 1 (tc) 4 i/o pt19d ? l11c_a0 l16c_a0 a14 b18 1 (tc) 4 i/o pt19c vref_1_04 l11t_a0 l16t_a0 d14 c20 1 (tc) ? v dd io1 v dd io1 ??? ? d18 1 (tc) 4 i/o pt19b ?? l17c_a0 ? e18 1 (tc) 4 i/o pt19a ?? l17t_a0 ? v19 ?? vss vss ??? m13 ??? v dd 15 v dd 15 ??? d13 b17 1 (tc) 5 i/o pt18d ptck1c l12c_a0 l18c_a0 c13 c17 1 (tc) 5 i/o pt18c ptck1t l12t_a0 l18t_a0 ? w16 ?? vss vss ??? ? d17 1 (tc) 5 i/o pt18b ?? l19c_a0 ? c18 1 (tc) 5 i/o pt18a ?? l19t_a0 b13 a16 1 (tc) 5 i/o pt17d ptck0c l13c_a0 l20c_a0 a13 b16 1 (tc) 5 i/o pt17c ptck0t l13t_a0 l20t_a0 ? e17 1 (tc) 5 i/o pt17a ??? a12 c16 1 (tc) 5 i/o pt16d vref_1_05 l14c_a0 l21c_a0 b12 d16 1 (tc) 5 i/o pt16c ? l14t_a0 l21t_a0 ? w17 ?? vss vss ??? ? a15 1 (tc) 5 i/o pt16a ??? c12 b15 1 (tc) 6 i/o pt15d ? l15c_a0 l22c_a1 d12 d15 1 (tc) 6 i/o pt15c ? l15t_a0 l22t_a1 ? c23 1 (tc) ? v dd io1 v dd io1 ??? ? a14 1 (tc) 6 i/o pt15a ??? b11 e16 1 (tc) 6 i/o pt14d ? l16c_a0 l23c_d1 a11 c14 1 (tc) 6 i/o pt14c vref_1_06 l16t_a0 l23t_d1 ? w18 ?? vss vss ??? ? b14 1 (tc) 6 i/o pt14a ??? d11 e15 0 (tl) 1 i/o pt13d mpi_rtry_n l1c_a0 l1c_a0 pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
62 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s c11 d14 0 (tl) 1 i/o pt13c mpi_ack_n l1t_a0 l1t_a0 a10 c4 0 (tl) ? v dd io0 v dd io0 ??? ? a13 0 (tl) 1 i/o pt13b ?? l2c_a0 c10 b13 0 (tl) 1 i/o pt13a vref_0_01 ? l2t_a0 b10 a12 0 (tl) 1 i/o pt12d m0 l2c_d0 l3c_a0 a9 b12 0 (tl) 1 i/o pt12c m1 l2t_d0 l3t_a0 ? w19 ?? vss vss ??? b9 d13 0 (tl) 2 i/o pt12b mpi_clk l3c_a0 l4c_a0 c9 e14 0 (tl) 2 i/o pt12a a21/mpi_burst_n l3t_a0 l4t_a0 d10 b11 0 (tl) 2 i/o pt11d m2 l4c_a0 l5c_a0 d9 a10 0 (tl) 2 i/o pt11c m3 l4t_a0 l5t_a0 ? d2 0 (tl) ? v dd io0 v dd io0 ??? a8 e13 0 (tl) 2 i/o pt11b vref_0_02 l5c_a0 l6c_a0 b8 d12 0 (tl) 2 i/o pt11a mpi_tea_n l5t_a0 l6t_a0 ? c11 0 (tl) 3 i/o pt10d ?? l7c_a0 ? b10 0 (tl) 3 i/o pt10c ?? l7t_a0 k13 ??? v dd 15 v dd 15 ??? ? a9 0 (tl) 3 i/o pt10a ??? a7 d11 0 (tl) 3 i/o pt9d vref_0_03 l6c_a0 l8c_d1 a6 b9 0 (tl) 3 i/o pt9c ? l6t_a0 l8t_d1 ? y13 ?? vss vss ??? ? a8 0 (tl) 3 i/o pt9a ??? c8 e12 0 (tl) 3 i/o pt8d d0 l7c_d0 l9c_d1 b7 c10 0 (tl) 3 i/o pt8c tms l7t_d0 l9t_d1 ? d3 0 (tl) ? v dd io0 v dd io0 ??? c7 d10 0 (tl) 4 i/o pt7d a20/mpi_bdip_n l8c_d0 l10c_a0 b6 c9 0 (tl) 4 i/o pt7c a19/mpi_tsz1 l8t_d0 l10t_a0 ? y14 ?? vss vss ??? d7 e11 0 (tl) 4 i/o pt6d a18/mpi_tsz0 l9c_a0 l11c_d1 d8 d9 0 (tl) 4 i/o pt6c d3 l9t_a0 l11t_d1 a5 e1 0 (tl) ? v dd io0 v dd io0 ??? ? a7 0 (tl) 4 i/o pt6b vref_0_04 ? l12c_a0 ? b8 0 (tl) 4 i/o pt6a ?? l12t_a0 c6 e10 0 (tl) 5 i/o pt5d d1 l10c_d0 l13c_d1 b5 c8 0 (tl) 5 i/o pt5c d2 l10t_d0 l13t_d1 b26 y15 ?? vss vss ??? ? b7 0 (tl) 5 i/o pt5b ?? l14c_a0 ? a6 0 (tl) 5 i/o pt5a vref_0_05 ? l14t_a0 a4 d8 0 (tl) 5 i/o pt4d tdi l11c_d1 l15c_d1 c5 b6 0 (tl) 5 i/o pt4c tck l11t_d1 l15t_d1 ? e3 0 (tl) ? v dd io0 v dd io0 ??? ? c7 0 (tl) 5 i/o pt4b ?? l16c_d1 ? a5 0 (tl) 5 i/o pt4a ?? l16t_d1 b3 c6 0 (tl) 6 i/o pt3d ? l12c_a0 l17c_a0 a3 b5 0 (tl) 6 i/o pt3c vref_0_06 l12t_a0 l17t_a0 k10 y20 ?? vss vss ??? pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 63 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ? e9 0 (tl) 6 i/o pt3b ?? l18c_d1 ? d7 0 (tl) 6 i/o pt3a ?? l18t_d1 d5 c5 0 (tl) 6 i/o pt2d pll_ck1c/ppll l13c_a0 l19c_a0 d6 d6 0 (tl) 6 i/o pt2c pll_ck1t/ppll l13t_a0 l19t_a0 ? e8 0 (tl) 6 i/o pt2b ?? l20c_a0 ? e7 0 (tl) 6 i/o pt2a ?? l20t_a0 b4 a4 ?? o pcfg_mpi_irq cfg_irq_n/ mpi_irq_n ?? b2 b4 ?? i/o pcclk cclk ?? k14 ??? v dd 15 v dd 15 ??? c4 e6 ?? i/o pdone done ?? c3 d5 ?? v dd 33 v dd 33 ??? k11 y21 ?? vss vss ??? ? ak26 ?? v dd 33 v dd 33 ??? ? p18 ?? v dd 15 v dd 15 ??? u13 ??? v dd 15 v dd 15 ??? ? p19 ?? v dd 15 v dd 15 ??? ? r16 ?? v dd 15 v dd 15 ??? ? r17 ?? v dd 15 v dd 15 ??? ? r18 ?? v dd 15 v dd 15 ??? ? r19 ?? v dd 15 v dd 15 ??? ? r34 ?? v dd 15 v dd 15 ??? ? t13 ?? v dd 15 v dd 15 ??? ? t14 ?? v dd 15 v dd 15 ??? ? t15 ?? v dd 15 v dd 15 ??? ? t20 ?? v dd 15 v dd 15 ??? ? t21 ?? v dd 15 v dd 15 ??? ? t22 ?? v dd 15 v dd 15 ??? ? t34 ?? v dd 15 v dd 15 ??? ? u13 ?? v dd 15 v dd 15 ??? ? u14 ?? v dd 15 v dd 15 ??? ? u15 ?? v dd 15 v dd 15 ??? ? u20 ?? v dd 15 v dd 15 ??? ? u21 ?? v dd 15 v dd 15 ??? ? u22 ?? v dd 15 v dd 15 ??? ? v13 ?? v dd 15 v dd 15 ??? ? v14 ?? v dd 15 v dd 15 ??? ? v15 ?? v dd 15 v dd 15 ??? ? v20 ?? v dd 15 v dd 15 ??? ? v21 ?? v dd 15 v dd 15 ??? ? v22 ?? v dd 15 v dd 15 ??? ? v34 ?? v dd 15 v dd 15 ??? ? w13 ?? v dd 15 v dd 15 ??? ? w14 ?? v dd 15 v dd 15 ??? ? w15 ?? v dd 15 v dd 15 ??? ? w20 ?? v dd 15 v dd 15 ??? pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
64 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s ? w21 ?? v dd 15 v dd 15 ??? ? w22 ?? v dd 15 v dd 15 ??? ? w34 ?? v dd 15 v dd 15 ??? ? y16 ?? v dd 15 v dd 15 ??? ? y17 ?? v dd 15 v dd 15 ??? ? y18 ?? v dd 15 v dd 15 ??? ? y19 ?? v dd 15 v dd 15 ??? ? aa16 ?? v dd 15 v dd 15 ??? ? aa17 ?? v dd 15 v dd 15 ??? ? aa18 ?? v dd 15 v dd 15 ??? ? aa19 ?? v dd 15 v dd 15 ??? ? aa34 ?? v dd 15 v dd 15 ??? ? ab16 ?? v dd 15 v dd 15 ??? ? ab17 ?? v dd 15 v dd 15 ??? ? ab18 ?? v dd 15 v dd 15 ??? ? ab19 ?? v dd 15 v dd 15 ??? ? ab34 ?? v dd 15 v dd 15 ??? ? ad33 ?? v dd 15 v dd 15 ??? ? ad34 ?? v dd 15 v dd 15 ??? ? ae34 ?? v dd 15 v dd 15 ??? ? ag33 ?? v dd 15 v dd 15 ??? ? ag34 ?? v dd 15 v dd 15 ??? ? ah34 ?? v dd 15 v dd 15 ??? ? ak29 ?? v dd 15 v dd 15 ??? ? al32 ?? v dd 15 v dd 15 ??? ? al33 ?? v dd 15 v dd 15 ??? ? al34 ?? v dd 15 v dd 15 ??? ? am31 ?? v dd 15 v dd 15 ??? ? am33 ?? v dd 15 v dd 15 ??? ? am34 ?? v dd 15 v dd 15 ??? ? an32 ?? v dd 15 v dd 15 ??? ? ap31 ?? v dd 15 v dd 15 ??? ? an34 ?? vss vss ??? ? ap1 ?? vss vss ??? ? ap4 ?? vss vss ??? ? ap33 ?? vss vss ??? ? ap34 ?? vss vss ??? ? y22 ?? vss vss ??? ? ap24 5 (bc) ? v dd io5 v dd io5 ??? ? ad1 7 (cl) ? v dd io7 v dd io7 ??? pin information (continued) table 20. pbga pinout table (continued) bm416 bm680 v dd io bank v ref group i/o pin description additional function bm416 pair bm680 pair
agere systems inc. 65 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s package thermal characteristics summary there are three thermal parameters that are in com- mon use: ja , jc, and jc . it should be noted that all the parameters are affected, to varying degrees, by package design (including paddle size) and choice of materials, the amount of copper in the test board or system board, and system airflow. ja this is the thermal resistance from junction to ambient (theta-ja, r-theta, etc.): where t j is the junction temperature, t a, is the ambient air temperature, and q is the chip power. experimentally, ja is determined when a special ther- mal test die is assembled into the package of interest, and the part is mounted on the thermal test board. the diodes on the test chip are separately calibrated in an oven. the package/board is placed either in a jedec natural convection box or in the wind tunnel, the latter for forced convection measurements. a controlled amount of power (q) is dissipated in the test chip ? s heater resistor, the chip ? s temperature (t j ) is deter- mined by the forward drop on the diodes, and the ambi- ent temperature (t a ) is noted. note that ja is expressed in units of c/watt. jc this jedec designated parameter correlates the junc- tion temperature to the case temperature. it is gener- ally used to infer the junction temperature while the device is operating in the system. it is not considered a true thermal resistance, and it is defined by: where t c is the case temperature at top dead center, t j is the junction temperature, and q is the chip power. during the ja measurements described above, besides the other parameters measured, an additional temperature reading, t c , is made with a thermocouple attached at top-dead-center of the case. jc is also expressed in units of c/w. jc this is the thermal resistance from junction to case. it is most often used when attaching a heat sink to the top of the package. it is defined by: the parameters in this equation have been defined above. however, the measurements are performed with the case of the part pressed against a water- cooled heat sink to draw most of the heat generated by the chip out the top of the package. it is this difference in the measurement process that differentiates jc from jc. jc is a true thermal resistance and is expressed in units of c/w. jb this is the thermal resistance from junction to board ( jl ). it is defined by: where t b is the temperature of the board adjacent to a lead measured with a thermocouple. the other param- eters on the right-hand side have been defined above. this is considered a true thermal resistance, and the measurement is made with a water-cooled heat sink pressed against the board to draw most of the heat out of the leads. note that jb is expressed in units of c/w, and that this parameter and the way it is mea- sured are still in jedec committee. fpsc maximum junction temperature once the power dissipated by the fpsc has been determined (see the estimating power dissipation sec- tion), the maximum junction temperature of the fpsc can be found. this is needed to determine if speed der- ating of the device from the 85 c junction temperature used in all of the delay tables is needed. using the maximum ambient temperature, t amax , and the power dissipated by the device, q (expressed in c), the max- imum junction temperature is approximated by: t jmax = t amax + (q ja ) figure 21 lists the thermal characteristics for all packages used with the orca orli10g fpsc. ja t j t a ? q ------------------- - = jc t j t c ? q -------------------- = jc t j t c ? q -------------------- = jb t j t b ? q ------------------- - =
66 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s package thermal characteristics table 21. orca orli10g plastic package thermal guidelines note: the 416-pin pbgam and the 680-pin pbgam packages include 2 oz. copper plates. heat sink vendors for bga packages the estimated worst-case power requirements for the orli10g with a programmable xgmii to xsbi interface for 10 gbits/s ethernet applications is 4 w to 5 w. consequently, for most applications an external heat sink will be required. below, in alphabetical order, is a list of heat sink vendors who advertise heat sinks aimed at the bga mar- ket. table 22. heat sink vendors package coplanarity the coplanarity limits of the agere packages are as follows: pbgam: 8.0 mils package ja ( c/w) max power 0 fpm 200 fpm 500 fpm t = 70 c max t j = 125 c max 0 fpm (w) 416-pin pbgam 18.0 16.5 13.5 3.05 680-pin pbgam 13.4 11.5 10.5 4.10 vendor location phone aavid thermal technology laconia, nh (603) 527-2152 chip coolers warwick, ri (800) 227-0254 ierc burbank, ca (818) 842-7277 r-theta buffalo, ny (800) 388-5428 sanyo denki torrance, ca (310) 783-5400 thermalloy dallas, tx (214) 243-4321 wafefield engineering wakefield, ma (617) 246-0874
agere systems inc. 67 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s package parasitics the electrical performance of an ic package, such as signal quality and noise sensitivity, is directly affected by the package parasitics. table 23 lists eight parasitics associated with the orca packages. these parasitics represent the contributions of all components of a package, which include the bond wires, all internal package routing, and the external leads. four inductances in nh are listed: l sw and l sl, the self-inductance of the lead; and l mw and l ml , the mutual inductance to the nearest neighbor lead. these parameters are important in determining ground bounce noise and inductive crosstalk noise. three capacitances in pf are listed: c m , the mutual capacitance of the lead to the near- est neighbor lead; and c 1 and c 2 , the total capacitance of the lead to all other leads (all other leads are assumed to be grounded). these parameters are important in determining capacitive crosstalk and the capacitive loading effect of the lead. resistance values are in m ?. the parasitic values in table 23 are for the circuit model of bond wire and package lead parasitics. if the mutual capacitance value is not used in the designer ? s model, then the value listed as mutual capacitance should be added to each of the c 1 and c 2 capacitors. table 23. orca orli10g package parasitics 5-3862(c)r2 figure 26. package parasitics package type l sw l mw r w c 1 c 2 c m l sl l ml 416-pin pbgam 3.52 0.80 235 0.40 1.0 0.25 1.5 ? 5.0 0.5 ? 1.30 680-pin pbgam 3.80 1.30 250 0.50 1.0 0.30 2.8 ? 5.0 0.5 ? 1.50 pad n l sw r w circuit board pad c m c 1 l sw r w l sl l mw c 2 c 1 l ml c 2 l sl pad n + 1
68 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s package outline diagrams terms and definitions basic size (bsc): the basic size of a dimension is the size from which the limits for that dimension are derived by the application of the allowance and the tolerance. design size: the design size of a dimension is the actual size of the design, including an allowance for fit and tol- erance. typical (typ): when specified after a dimension, this indicates the repeated design size if a tolerance is specified or repeated basic size if a tolerance is not specified. reference (ref): the reference dimension is an untoleranced dimension used for informational purposes only. it is a repeated dimension or one that can be derived from other values in the drawing. minimum (min) or maximum (max): indicates the minimum or maximum allowable size of a dimension.
agere systems inc. 69 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s package outline diagrams (continued) 416-pin pbgam dimensions are in millimeters. 1139(f) 0.61 0.08 1.17 0.05 2.28 0.10 seating plane solder ball 0.50 0.10 0.20 27.00 27.00 24.00 24.00 pin a1 corner af ae ad ac ab aa y w v u t r g 25 spaces @ 1.00 = 25.00 p n m l k j h 1 2 3 4 5 6 7 8 9 10 12 14 16 18 22 24 26 20 11 13 15 17 21 19 23 25 f e d c b a center array for thermal enhancement 25 spaces @ 1.00 = 25.00 a1 ball corner 0.63 0.15
70 agere systems inc. data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s package outline diagrams (continued) 680-pin pbgam dimensions are in millimeters. 5-4406(f) seating plane solder ball 0.50 0.10 0.20 35.00 t d h al f k b p m l j ah r c e y n u an g ad v am aj ag ae ac aa w ap ak af ab a 19 30 26 28 24 32 22 20 18 4 6 8 10121416 2 34 52325 731 29 15 21 327 11 17 913 1 33 33 spaces @ 1.00 = 33.00 33 spaces a1 ball 0.64 0.15 a1 ball @ 1.00 = 33.00 corner 30.00 1.170 + 0.70 ? 0.00 35.00 30.00 + 0.70 ? 0.00 identifier zone 2.51 max 0.61 0.08
agere systems inc. 71 data sheet october 2001 10 gbits/s, and 12.5 gbits/s line interface fpsc orca orli10g quad 2.5 gbits/s hardware ordering information 5-6435 (f).q orli10g, ? 1 speed grade, 680-pin plastic ball grid array multilayer (pbgam). table 24. device type options table 25. temperature options table 26. package options table 27. package matrix (speed grade) software ordering information implementing a design in an orli10g fpsc requires the orca foundry development system and an orli10g design kit. for ordering information please visit: http://www.agere.com/micro/netcom/ipkits device voltage orli10g 1.5 v internal symbol description temperature (blank) industrial ? 40 c to +85 c symbol description bm plastic ball grid array, multilayer (pbgam) devices 416-pin pbgam 680-pin pbgam orli10g ? 1, ? 2, ? 3 ? 1, ? 2, ? 3 device type package type orli10g -1 bm number of pins 680 speed grade temperature range
copyright ? 2001 agere systems inc. all rights reserved october 2001 ds01-277ncip (replaces ds01-269ncip) agere systems inc. reserves the right to make changes to the product(s) or information contained herein without notice. no liab ility is assumed as a result of their use or application. orca is a registered trademark of agere systems inc. foundry is a trademark of xilinx. for additional information, contact your agere systems account manager or the following: internet: http://www.agere.com or for fpgas/fpscs http://www.agere.com/orca e-mail: docmaster@agere.com n. america: agere systems inc., 555 union boulevard, room 30l-15p-ba, allentown, pa 18109-3286 1-800-372-2447 , fax 610-712-4106 (in canada: 1-800-553-2448 , fax 610-712-4106) asia: agere systems hong kong ltd., suites 3201 & 3210-12, 32/f, tower 2, the gateway, harbour city, kowloon tel. (852) 3129-2000 , fax (852) 3129-2020 china: (86) 21-5047-1212 (shanghai), (86) 10-6522-5566 (beijing), (86) 755-695-7224 (shenzhen) japan: (81) 3-5421-1600 (tokyo), korea: (82) 2-767-1850 (seoul), singapore: (65) 778-8833 , taiwan: (886) 2-2725-5858 (taipei) europe: tel. (44) 7000 624624 , fax (44) 1344 488 045 ieee is a registered trademark of the institute of electrical and electronics engineers, inc. eia is a registered trademark of electronic industries association. pal is a trademark of advanced micro devices, inc. powerpc is a registered trademark of international business machines, inc. amba is a trademark and arm is a registered trademark of advanced risc machines limited. synopsys smart model is a registered trademark of synopsys, inc. motorola is a registered trademark of motorola, inc.

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